Newsletter May 2009
The OpenRISC processor project has a brand new project-website and its SVN repository has received a clean out.
The OpenRISC processor was the first project at OpenCores when it began in 1999. Over the years it has been continuously growing, and as a result of this we needed to develop an external web-page for the OpenRISC processor since it comprises of many elements (hardware, software toolchain, operating system, test systems, etc.).
The original CVS repository has also grown a lot and we felt that it was time to "clean-up" and get rid of "old obsolete items". The new OpenRISC SVN repository contains the following:
- OR1200 RTL (OpenRISC OR1200 Verilog design)
- ORPSOC (OpenRISC reference design and Test Suite)
- GCC (GNU C-compiler)
- GDB-6.8 (GNU debugger)
- JTAG-proxy-debug-SW (OpenRISC processor debugger via JTAG)
- OR1K-start-up (Verilog module handle coldstart of the OpenRISC processor from a SPI FLASH)
- Linux-2.6.23 (Ported for the OpenRISC processor)
- eCos (Ported for the OpenRISC processor)
- RTEMS (Ported for the OpenRISC processor)
- HW-platform (A modular FPGA development board running the ORPSOC reference design)
Link to the "new" OpenRISC page: click here
The "old" repository is still available (read only mode) so that users can checkout older versions. No additional development will occur in this repository.
The OpenRISC Reference Platform SoC (ORPSoC) and it's Test Suite has received an update. Now supported is the Icarus Verilog simulator, and generation of a cycle-accurate model (using Verilator).
ORPSoC is the OpenRISC processor test-system, it consists of an OR1200 processor reference design together with an extensive test-system. The test-cases are either C-code or assembler which are then compiled by GCC and then executed in the design. The system is monitored and its behavior is checked to ensure it is correct. There are today several test-programs (test suites) testing different areas in the processor.
The scripts have been enhanced, making use of the latest GNU toolchain, the Icarus Verilog simulator (open-source), and Cadence NCSIM. Also new to this latest ORPSoC (v2) is support for generating a cycle-accurate model of the system using Verilator, resulting in a much faster but less complex simulation model.
Link to the ORPSoC page: click here
There has been a new addition to the forums on OpenCores. This new forum now provides a place where users can ask more "generic"-questions or "design help"-questions.
Since the existing forums at OpenCores require the posts/questions to be related to an existing IP cores at OpenCores, we have now added a new forum where users can post more "generic" posts/questions.
The new forum is named: "Other"
Link to the Forum page: click here
It’s possible to subscribe to this forum. This option is available under "My account settings".
This topic gives you an update of what has been "cooking" at the OpenCores community during the last month and a communication channel.
This month activities:
Still fixing website bugs
We are still fixing minor bugs and the system is now very stable, apart from a disk-failure that caused a file system error. This forced us to switch to our backup-server (staging server). We plan to switch back within a couple of days.
Designing the "new" OpenRISC-page
A lot of our effort during this past month has been to create the "new" OpenRISC project page and to "clean up" the SVN repository.
Our message to the community:
Keep everyone updated of your project.
Make sure everyone knows about your project and what is going on with it. The number one thing is to make sure you have a good description of the project including text and perhaps some pictures. This makes it easier for visitors to get an overview of the project and understand if this is what they are looking for. This is also the only way you can make your project visible for all search engines. It is also important that you fill in all relevant information about the project, such as license information (see below), Status, Updates (see below), etc.
Projects Update information
To make it easier for all users to find information about what is happening within different projects it is important that all updates are commented. Please write a few lines within the project's "news" page for all updates you do – let everyone know if it is just a correcting of a misspelled projects description or of it is a major update of the RTL code in the SVN repository.
We have written about open source EDA tools in the previous newsletters. This has been a very popular theme and we have received information about some other popular tools. Please read more about them in the list below.
Verilator is a free Verilog HDL simulator. It compiles synthesizable Verilog into an executable format and wraps it into a SystemC model. Internally a two-stage model is used. The resulting model executes about 10 times faster than standalone SystemC.
Verilator has been used to simulate many very large multi-million gate designs with thousands of modules. Therefore we have chosen this tool to be used in the verification environment for the OpenRISC processor (ORPSoC environment).
TCE is a toolset for designing application-specific processors (ASP) based on the Transport triggered architecture (TTA). The toolset provides a complete co-design flow from C programs down to synthesizable VHDL and parallel program binaries. Processor customization points include the register files, function units, supported operations, and the interconnection network.
TCE has been developed internally in the Tampere University of Technology since the early 2003. The current source code base consists of roughly 400 000 lines of C++ code.
C to Verilog translation
Available is an online C to Verilog compiler. The code generated by the site is licensed under BSD (use it "as is").
C to Verilog website
Fedora Electronic Lab
Fedora Electronic Lab tries to provide a complete hardware design flow with the best opensource tools. We try to ensure interoperability as far as we can and we work with other opensource developers to improve existing EDA tools.
Fedora Electronic Lab website
UrJTAG aims to create an enhanced, modern tool for communicating over JTAG with flash chips, CPUs, and many more. This tool also supports configuration of FPGA from SVF files.
This software package provides a command line tool for documenting hardware and software designs through timing diagrams. It reads signal descriptions from a text file with an intuitive syntax, and outputs a timing diagram to an image file. Notation typical of timing diagrams found in the Electrical Engineering discipline is used, including arrows indicating causal relationships between signal transitions. The project is hosted on Sourceforge
View a list of some of the projects that has been updated during the last month. Here you will also see new interesting projects that have reached a first stage of development.
USB FPGA module 1.2
Phase: Design done, Specification done
Alwcpu - A light weight CPU
Alwcpu is a light weight CPU in terms of logic resources.
- 16 bit address and data bus. (Instructions are 16 bit as well)
- Wishbone interface
- Is parameterizable to optimize size, e.g. skipping of instruction groups, selectable 8 or 16 registers...
- Assembler will be available.
Advanced Debug System
The Advanced Debug Interface is a suite of IP cores and software programs designed to allow a developer to download code to a target CPU in a System-on-Chip, then perform source-level debugging of that code. In particular, target systems using the OpenRISC 1200 processor and a WishBone bus are currently supported by the Advanced Debug Interface.
Development status: Beta
-Maximum 4 by 4 Tiles
-The synchronizing FIFO
-Virtual channel(3 stage buffer)
-User reconfigure PE(Processing element)'s program
Development status: Planning
System-on-Chip Wire (SoCWire)
It is a Network-on-Chip (NoC) approach based on the ESA SpaceWire interface standard to support dynamic reconfigurable System-on-Chip (SoC). SoCWire has been developed to provide a robust communication architecture for the harsh space environment and to support dynamic partial reconfiguration in future space applications.
PPhazes: Design done, Specification done
SD card controller
The "sd card controller" is an SD/MMC communication controller which aims to provide a fast and simple interface to SD/MMC cards. One of the main goals of this project is that the controller should be usable as a system disk, containing a file system. Therefore the core has been developed with features that assist in this. The design also includes a simplified model of a SD-card to test against.
Phases :: Design done, Specification done
Yet another VGA
This core is a simple and small VGA controller.
- It drives vga monitors with an 800x600 resolution and 72Hz vertical refresh rate (50MHz pixel clock)
- It displays chars on the screen (each char is 8x16 pixels)
- It has a customizable charset (you can use a simple text editor in order to "visually" customize it)
- It can display a color "waveform"
- It can display a color grid and "cross cursor"
Phases: FPGA proven
The aim of the OpenRISC project is to create a free, open source 32 bit RISC processor available under the LGPL license. Platform must be versatile to fit various target applications.
Phase: ASIC proven
A 6507-compatible microprocessor is being developed. It will be used in a SoC that targets the ATARI 2600 system. RIOT(MOS 6532) and TIA chips will be developed to complete the entire system.
Phases: Design done, Specification done
32 Bit RISC Processor, 5 Stage Pipeline. Developed for embedded control of devices.
Development status: Alpha
Simple AES3 / SPDIF receiver
AES3 / SPDIF receiver is simple, minimalistic but powerful core which decodes biphase mark coded AES3 compatible signal and retransmitts it in I2S-like format.
Phases: Design done