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NEWSLETTER JUNE 2010

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Updated OR1200 processor available

The team from OpenCores and ORSoC are very pleased to announce the release of the updated OpenRISC OR1200 processor (release 3).
This OpenRISC update together with the Linux 2.6.34 will take the OpenRISC platform to the next level....

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Implementation statistics.

New web service available for OpenCores projects. The service implements any Verilog/VHDL IP core across popular FPGAs/CPLDs, and tells developers which programmable logic devices meet their IP's requirements like size, speed and power consumption.
implementation stastistics, OpenCores.org

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Update of the Wishbone system interconnect specification

The widely used Wishbone system interconnect bus have been updated to revision B4. This new release adds a pipelined traffic mode, which will significantly increase the performance especially when used in combination with external bus bridges and with high latency peripherals such as SDRAM memories...

Read more...


Update from OC-Team

This topic gives you an update of what has been "cooking" at the OpenCores community during the last month.
- Added a separate SVN server
- Upgraded to larger harddisks

Read more...


New IP-cores at OpenCores

View a list of all interesting new projects that have reached a first stage of development.

Read more...


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Newsletter May 2010


OpenRISC Announcement - updated RTL is now available

The team from OpenCores and ORSoC are very pleased to announce the release of the updated OpenRISC OR1200 processor (release 3).

The update will include several bug fixes and generic improvements that was discovered during the Linux 2.6.34 porting activity. This OpenRISC update together with the Linux 2.6.34 will take the OpenRISC platform to the next level.

By improving the OpenRISC processor and enabling support for the latest and greatest from the world of open-source OSes and libraries for the OpenRISC platform we hope to see increased uptake and participation in the project from all. The team at OpenCores are forever tweaking and improving parts of the implementations that exist, allowing them to be used with greater ease and reliance.

We hope to generate further interest in the OpenRISC project, and potentially gain new contributors and supporters of the platform. We expect that by updating the OR1200 processor we will see increased uptake of the technology and greater participation from the community. As well as this, we hope to release further tools and documentation that will help people get started with the OpenRISC platform.

There are always problems inherent in aiming for software reuse, however the combination of reusable IP and driver software essentially results in a two-for-one deal. Considering the attention the software development receives in modern designs, it's good to know that when using highly portable open-source IP and low-level drivers, they start off on an effective and dependable note.

So feel free to join us and help us continue improving the OpenRISC processor, verification is for example always needed and highly appreciated. More information howto download the RTL click here





Update of the Wishbone system interconnect specification

The widely used Wishbone system interconnect bus have been updated to revision B4. This interconnect standard is used to interconnect many of the popular IP cores available at OpenCores and is also used in a large number other designs. The flexibility and ease of use in combination to the license model have been the key to the success of this standard. Wishbone is the preferred interconnect standard used at OpenCores.

This new release, B4, adds a pipelined traffic mode. This will significantly increase the performance especially when used in combination with external bus bridges and with high latency peripherals such as SDRAM memories.

For those familiar with the wishbone interface the following gives a brief description of the update

  • master does not wait for ACK before outputting next address/data word on the bus
  • an introduced signal STALL indicates that the slave cannot accept another request at the moment
  • master outputs requests as long as STALL is deasserted, when STALL is asserted it waits
  • cycle consisting of N transactions are terminated with a sequence of N acknowledges
  • read data is valid when ACK is asserted

The Wishbone B4 specification is available here

The update is done by ORSoC and based on an idea from Tomasz Wlostowski working at CERN





Update from OC-Team

This topic gives you an update of what has been "cooking" at the OpenCores community during the last month.

This month activities:

Website information:

  • Changed the system so that the SVN server is running on a separate server in order to decrease the load on the webserver
  • Added Plunify design information to OCCP approved projects


Server information:

  • Added a separate SVN server
  • Upgraded to larger harddisks


Our message to the community:

  • Please try to upgrade your projects to reach the OCCP level (OpenCores Certified Projects), read more about what is needed of your project to achieve this in FAQ-Projects.





New IP-cores

Here you will see interesting new projects that have reached the first stage of development.

Reed-Solomon Decoder
This project implements a parameterized Reed Solomon decoder for use in OFDM wireless systems. Source code provided in C++ (trunk/cpp-source) and Bluespec(trunk/bluespec-source).
Development status: Stable
License: LGPL
Updates:
Jun 16, 2010: Changing language tag to reflect dual source code
Jun 16, 2010: Initial commit of source code for Reed-Solomon decoder in Bluespec and C++

opb_usblite
opb_usblite - opb_uartlite replacement for Xilinx Microblaze processor written in VHDL and Verilog. The opb_usblite is compatible with the USB CDC profile and works with microsoft usbser virtual comport driver (VCD).
Development status: Alpha
License: LGPL
Updates:
Jun 6, 2010: Added Misc info
Jun 6, 2010: Software/Driver info added
Jun 5, 2010: Implementaion details added
Jun 2, 2010: Updated project description

SpaceWire Light
SpaceWire Light is a SpaceWire encoder-decoder with FIFO interface. It is synthesizable for FPGA targets (up to 200 Mbit on Spartan-3).
The goal is to provide a complete, reliable, fast implementation of a SpaceWire encoder-decoder according to ECSS-E-50-12C. The core is "light" in the sense that it does not provide additional features such as RMAP, routing etc.
Development status: Alpha
License: LGPL
Updates:
Jun 8, 2010: setting up project page

CPU Code Execution Timestamp
A fabric coprocessor module (FCM) for the PowerPC 405 CPU providing code execution timestamp, allowing to measure precisely CPU code execution times.
Development status: Mature
License: LGPL
Updates:
Jun 11, 2010: upload

Nugroho Free Hash Cores
Nugroho Free Hash Cores (NFHC) currently support SHA-1, SHA-256, SHA-512 from FIPS-180 standard.
Development status: Alpha
License: BSD
Updates:
Jun 24, 2010 Update NFHC project information.

ratpack
"ratpack" is a rational arithmetic package written in VHDL.
Development status: Beta
License: LGPL
Updates:
Jun 7, 2010: README information

Open JTAG project
The Open JTAG project has as objetive to give to the public domain a complete hardware and software JTAG project. Based on a simple hardware board, composed basically by a FT245 USB front end and an Altera EPM570 MAX II CPLD, this board is capable to output TCK signal at 24 MHZ using macro-instructions sent from the computer end.
It is not as others JTAG projects based on the PC parallel port: Open JTAG project uses the USB channel (still not at full speed) to communicate with the internal CPLD, sending macro-instruction as fastest as possible.
Development status: Beta
License: LGPL
Updates:
Jun 19, 2010: Description
Jun 1, 2010: Initial upload





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