OpenRISC development board from ORSoC

ARMSoC-FPGA System-on-Module

Designed for products requiring processor systems combined with programmable logic, providing a very flexible hardware platform at lowest cost possible.


Altera Shipping Industry’s Fastest Backplane-capable Transceivers

Industry’s Only FPGA with 14.1 Gbps Backplane-capable Transceivers to Meet High-Performance Requirements in Test and Measurement, Data Centers and Storage Area Networks.


Update from OC-Team

This topic gives you an update of what has been "cooking" at the OpenCores community during the last month.


New IP-cores at OpenCores

View a list of all interesting new projects that have reached a first stage of development.
This month: 8 new projects


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Newsletter June 2012

ARMSoC-FPGA System-on-Module

The ARMSoC-FPGA System-on-Module is complete processor system consisting of processor, USB hub, power management and a powerful large FPGA offered as a low cost product, enabling cost-effective product development.

ARMSoC-FPGA System-on-Module product, developed by ORSoC
Board dimensions: 68mm x 68mm

The module is using a SO-DIMM interface, making it easy to tailor the product with appropriate external interfaces and connectors. This modular system enables product companies too use this module in multiple products, providing the following benefits:

- Lower unit cost due to higher volumes as a result of using it in several products.
- Rapid development cycle. The IO-board is often much simpler to develop, saving both valuable development time and costs.
- Knowledge/experiance. Re-using the same platform for multiple products lead to higher knowledge, higher quality and faster development.
- Possibility to upgrade the ARMSoC-FPGA module without impacting the IO-board.

Due to its large flexibility and its tight connection directly to a large 22K LUT Altera FPGA, the module supports a wide range of product applications, for example:

- Distributed IO systems
- Industrial controllers
- Ethernet switching systems
- Data capturing systems
- Supervision/Monitoring systems
- Cryptography systems

ARMSoC-FPGA System-on-Module product, developed by ORSoC

The three devices (FPGA, Micrel SoC, USB) are all connected via a PCI interface, which is a multi-master bus allowing all connected devices access each other's internal functions. The FPGA can for example act as a hardware accelerator to the ARM processor, off loading the processor and increasing the system performance. This also means lower power consumption compared to other solutions using faster processor solutions.

The SO-DIMM interface is a common and cost-effective interface to an IO-board hosting the desired peripherals. This also makes it possible to effectively be able to upgrade / modify the system depending on peripheral requirements.

This board is available from September 2012.
The board will be sold via OpenCores webshop. For volume orders, please contact ORSoC via or +46 8 24 84 04.

ARMSoC-FPGA System-on-Module technical details:

- ARM922 at 167MHz
- 8KB I-cache and 8KB D-cache
- 32 bit ARM and 16 bit thumb instruction set

Ethernet Transceivers and Switch Engine
- Five 10/100 Ethernet transceivers and five MACs (1 Port WAN, 4 Ports LAN )
- 100BASE-FX mode option on the WAN and one LAN port
- Wire speed, non blocking switch
- 802.1Q tag based VLAN
- Port based VLAN
- IGMP snooping

USB 2.0 high-speed HUB
- EHCI host controller
- root HUB with 5 downstream facing ports

- 22K LUT
- 40 Multipliers 18x18
- 4 high speed transceivers; PCI Express (PCIe), Gbps Ethernet (GbE)

Interface to external IO-board
- SO-DIMM 200 pin

- USB, 5V or single cell Li-ion or Li-polymer
- Battery charger

PCB-layout tool
For this project we tested a new PCB-layout tool from a company called Altium, the tool is called “Altium designer” and it's a complete EDA tool covering all aspects/functions that is needed to develop a electronic product. A very exciting functions is the connection between the PCB-layout tool and their FPGA development tool. We are very impressed with the tool and recommend you to try it out, click here for more infomation about the Altiums tool.

ORSoC-team, ORSoC

Altera Shipping Industry’s Fastest Backplane-capable Transceivers in 28-nm Stratix V FPGAs

San Jose, Calif., July 31, 2012—Altera Corporation (Nasdaq: ALTR) today announced it is shipping in volume production the FPGA industry’s highest performance backplane-capable transceivers. Altera’s Stratix® V FPGAs are the industry’s only FPGAs to offer 14.1 Gbps transceiver bandwidth and are the only FPGAs capable of supporting the latest generation of the Fibre Channel protocol (16GFC). Developers of backplanes, switches, data centers, cloud computing applications, test and measurement systems and storage area networks can achieve significantly higher data rate speeds as well as rapid storage and retrieval of information by leveraging Altera’s latest generation 28-nm high-performance FPGA. For OTN (optical transport network) applications, Stratix V FPGAs allow carriers to scale quickly to support the tremendous growth of traffic on their networks.

Altera started shipping engineering samples of 28-nm FPGAs featuring integrated 14.1 Gbps transceivers over one year ago. These high-performance devices are the latest in Altera’s 28-nm FPGA portfolio to ship in volume production. The transceivers in Stratix V GX and Stratix V GS FPGAs deliver high system bandwidth (up to 66 lanes operating up to 14.1 Gbps) at the lowest power consumption (under 200 mW per channel). Transceivers in Altera’s FPGAs are equipped with advanced equalization circuit blocks, including low-power CTLE (continuous time linear equalization), DFE (decision feedback equalization), and a variety of other signal conditioning features for optimal signal integrity to support backplane, optical module, and chip-to-chip applications. This advanced signal conditioning circuitry enables direct drive of 10GBASE-KR backplanes using Stratix V FPGAs.

“Developers of next-generation protocols need to leverage the latest test equipment that integrates the latest technologies,” said Michael Romm, vice president of product development, at LeCroy Protocol Solutions Group, a leading manufacturer of test and measurement equipment. “Altera’s latest family of 28-nm FPGAs gives us the capability to build the most sophisticated and advanced test equipment so our customers can rapidly develop and bring to market their next-generation systems.”

Published by Altera, click here to read the whole article.

Update from OC-Team

This topic gives you an update of what has been "cooking" at the OpenCores community during the last month.

This month activities:

Website information:

  • Some minor issues

Server information:

  • Running very smoothly.

Our message to the community:

  • Help us improve the community, please provide feedback

Marcus Erlandsson, ORSoC

New IP-cores

Here you will see interesting new projects that have reached the first stage of development.

The PCIe_DS_DMA core provides PCI Express controller for Xilinx HARD core for Virtex5, Virtex6, Spartan6 FPGA.

Main features
- PCI Express 1.1 x1,x4,x8 or 2.0 x4
- two address space: BAR0, BAR1
- access to registers can only be single 32-bit instructions
- local bus: 64 bit, 250 MHz
- two independent bidirectional DMA channel
- DMA channel only works in the SCATTER-GATHER mode
- The minimum unit of data for channel DMA - 4 kB
- Descriptors combined into the block descriptors. The maximum number of descriptors in the block - 63
- DMA channel uses 40 bit addresses

Development status: Alpha
License: LGPL
Aug 13, 2012: add results of data transfer
Aug 11, 2012: description update
Aug 10, 2012: description update

PDP-8 Processor Core and System
The PDP-8 was one of the earliest minicomputers and was in use from the mid 1960s into the 1980s.

Because the PDP-8 was relatively inexpensive and was available in various forms for many years, the PDP-8 is remembered fondly by many programmers and engineers

This project implements a complete PDP-8 system. The system includes the many of the basic PDP-8 peripherals including:

- Configurable PDP-8 CPU
- MS8C 32K-word memory
- KC8E Front Panel
- KE8 Extended Arithmetic Element
- KM8E Extended Memory
- KM8E Time Sharing
- DK8EA/DK8EC/DK8EP Real Time Clock
- KL8E Asynchronous Serial Interface (x2)
- LS8E Printer Interface
- PR8E Paper Tape Reader
- KL8E Disk Controller with 4 RK05 Disks Attached

Development status: Alpha
License: GPL
Jul 11, 2012: Added more to the quick start guide.
Jul 11, 2012: Added text about ordb2a-ep4ce22 implementation
Jul 11, 2012: Added info on OS/8
Jul 10, 2012: Added links for disk images
Jul 10, 2012: Added SD card compatibility note
Jul 10, 2012: Starting a quick start guide for new users
Jul 10, 2012: Added implementation information
Jul 10, 2012: More updates to summary.
Jul 10, 2012: Updated features section, again.
Jul 10, 2012: Updated features
Jul 10, 2012: Added project description

PID controller
The PID controller IP core performs digital proportional–integral–derivative controller (PID controller) algorithm. The algorithm first calculates the error between a measured value (PV) and its ideal value (SP), then use the error as an argument to calculate the manipulate value(MV). The MV will adjust the process to minimize the error. It can be used to calculate duty cycle for PWM (Pulse Width Modulation).

• 16-bit signed coefficient and data input: Kp, Ki, Kd, SP and PV.
• 32-bit signed u(n) output.
• Containing one high speed 32-bit prefix-2 Han-Carlson adder and one high speed pipelined 16x16-bit multiplier.
• Latency from input of PV to finished calculation and update of u(n) is 17 clock cycles.
• Ki, Kp, Kd, SP, PV can be updated anytime after reset.
• After every update of Kp or Kd, register Kpd which stores Kp+Kd will be calculated and updated.
• After every update of PV, calculation and update of e(n), e(n-1), sigma and u(n) will be triggered in sequence.
• Overflow register records overflow signals when calculating Kpd, e(n), e(n-1), u(n) and sigma.
• Using 2278 of 4608 (49%) Core Cells in Actel A2F200M3F FPGA and running at 100MHz clock frequency.
• Wishbone B4 compliant interface. Support 16-bit, 32-bit and 64-bit bus width.

Development status: Stable
License: LGPL
Jul 11, 2012: add description
Jul 10, 2012: project set up

SATA PHY layer which can be implemented as either a host or device for Xilinx 6 series devices.
Development status: Stable
License: LGPL
Jul 12, 2012: New SATA PHY core.
Jul 12, 2012: New SATA PHY core.

EtherLab - Spartan-3E StarterKit To C# To Bridge
EtherLab sends data via Ethernet packets from the Spartan-3E StarterKit to a host PC or vice versa.

The transport protocol is the name giving EtherLab protocol, that comes directly after the Ethernet layer. An EtherLab layer provides 8 seperate channels each transporting 16 bit of data.

The hardware reads and sends EtherLab packets only and communicates with the 4 D/A Converters, LEDs, swithes, buttons, digital inputs and outputs.

EtherSocket is a C# implementation based on Pcap.Net and provides the bare minimum functions to read and send EtherLab datagrams. Incomming data is read constantly in a seperate thread. To send data, the user first updates at least one channel and sends the entire updated packet afterwards.

The C# EtherSocket implementation has been ported to LabVIEW. Polymorphic VIs provide custom read and update operations for Booleans and Floats.
Development status: Beta
License: GPL
Jul 20, 2012: download link
Jul 20, 2012: docs

This is a structural modeling for IIR digital filters. It is developed in SystemC, however, it includes Matlab script and Simulink model as well. The developed code describes several structures for IIR filters, such as Transposed-form I, Transposed-form II, and Direct-form II. The implemented structures are well defined in the attached manual. Further, the detailed implementation is illustrated on the later file.
Development status: Beta
License: GPL
Jul 20, 2012: uploading and documenting

Salsa20 stream cipher is built on a pseudorandom function based on 32-bit addition, bitwise addition (XOR) and rotation operations, which maps a 256-bit key, a 64-bit nonce (number used once), and a 64-bit stream position to a 512-bit output. It has advantage that the user can efficiently seek to any position in the output stream.
Development status: Mature
License: LGPL
Jul 28, 2012: First working version of VHDL code uploaded.
Jul 19, 2012: Added project description.

This project is developed at Reconfigurable Computer Laboratory - FRM - UTN, and allows simulate and synthesize the Gregory-Newton extrapolation algorithm, using integer numbers.
Development status: Beta
License: GPL
Aug 14, 2012: Beta.
Aug 14, 2012: The project's files was added.

16x2 LCD controller
Controller for 16 character - 2 line LCD displays as used on various Xilinx evaluation boards.

- 4-bit LCD data interface
- One 128bit-wide std_logic_vector input for each diplay line (16x8bit=128). Everything you send to those inputs goes directly to the display.

- Tested on Xilinx ML501 and ML507
- Virtex5: 37 flip flops, 228 LUTs, >300MHz

Development status: Stable
License: LGPL
Aug 4, 2012: Updated project status
Aug 4, 2012: Project status updated.
Jul 30, 2012: Project moved to category "Others".
Jul 29, 2012: Initial upload.

Johan Rilegård, ORSoC

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