OpenRISC development board from ORSoC

"OpenRISC inside"
Commercial product based on the OpenRISC processor

The TMC01 module - an industrial control system product developed for Invensys Systems GmbH by ORSoC.
In this article we will present the product and how it's using open source IPs from


+1000 projects available via OpenCores

During Januari 2013 we reached over 1000 project available via OpenCores.
The last year the number of newly started projects has increased rapidly. We are very pleased by this progress and certainly hope that most of the new projects will stay active and within shortly end up in ready, well designed IPs.

Update from OC-Team

This topic gives you an update of what has been "cooking" at the OpenCores community during the last month.


New IP-cores at OpenCores

View a list of all interesting new projects that have reached a first stage of development.
This time: 9 new projects


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Newsletter January 2013

"OpenRISC inside" - Commercial product based on the OpenRISC processor

Commercial product based on IP's from

The TMCO1 module from Invensys Systems GmbH is a product targeted for the industrial control systems, allowing existing system to connect to state-of–the-art Ethernet Mesh Control Network. Bridging Tokenbus based system to 100FX systems.

The product is based on an OpenRISC OR1200 processor from and are running Linux. Using an OpenRISC based System-On-Chip solution provides a future-proof solution that can easily be ported to other FPGA devices, if needed.

ORSoC has been responsible for the whole development project, providing FPGA design, PCB design, Software design and Production. This is a complex product, but thanks to open source technology from OpenCores in combination with technical expertise from ORSoC the development has been very efficient and the product is now available on the market.

Picture of the TMCO1 module:

TMCO1 PCB module - Invensys - developed by ORSoC - OpenRISC processor inside

Block schematic of the PCB and FPGA:

TMCO1 block schematic - Invensys - developed by ORSoC - OpenRISC processor inside

FPGA provides the following functionality:
- OpenRISC OR1200 processor running Linux
- 2 x Ethernet MAC
- 2 x Tokenbus MAC
- SDRAM controller
- SPI Flash controller
- Wishbone System-on-Chip bus arbiter

Information from Invensys Systems GmbH about this product and its usage.

TMC01 Moduls (Token-Mesh Converter) for the Foxboro PLS80E System-Bus connect redundant Controllers CM23 and CX21 with the Mesh Control Network. Overview

The Foxboro PLS80E Automation system depends on the established Eckardt PLS 80 System and will be continuously upgraded, according to the commitment of Invensys to customers for life cycle support. Invensys utilises Mesh Control Networks for Automation-Systems.
By this way now the PLS80E Token-Bus System will be upgraded to a state-of–the-art Ethernet Mesh Control Network.
The Mesh Control Network replaces both the PLS80E System-bus and the PLS80E Function-bus. To this Bus the new controllers CX22 will be direct connected.

The TMC01 is designed to connect also the older controllers PLS 80E controller CX21 and CM21 to the Mesh Network and therefore to integrate older modules with new components for a sufficient life cycle concept. TMC01 modules replace plug-compatible previous necessary bus connectors and can also used in redundant configurations.
The TMC01 modules start automatically after plug-in on the system-rack, no configurations are necessary. Replacement will be done on-line. Software Updates for the TMC01 will be done ‘remote and on-line’ from an Engineering station.

Together with a Mesh Control Network there are also available network-monitors as Nagios or similar.
These functions not only control cyclic the Mesh Control Network, but also the communication level of the connected controllers. By this way preventive maintenance will be possible.

TMCO1 module network - Invensys

About Invensys Systems GmbH

Invensys Operations Management is a leading provider of automation and information technologies, systems, software solutions, services and consulting to global manufacturing and infrastructure industries. The marketplace knows us from our premier brands – Avantis, Eurotherm, Foxboro, IMServ, InFusion, SimSci-Esscor, Skelta, Triconex and Wonderware. Our solutions, which are used by more than 40,000 clients in over 200,000 plants and facilities around the world, include control and measurement instrumentation; safety, critical and distributed control systems; a wide range of real-time operations management software and professional services.

Contact information:
Invensys Systems GmbH website

Information from ORSoC about this product and its usage
This has been an exiting project due to the fact it involves all parts of a product development: FPGA development, PCB design, SW design, testing and production. With our tools, predesigned platforms and extensive experience we have been able to very efficient run this project from start to finish.

The last couple of years ORSoC have gain many projects where we handle most of the development for our customers. We are very pleased that our customers appreciate our design expertise and huge experience from designs based on IPs from OpenCores. We also handle more and more long time support projects.

We will try to present as many of these projects a possible in the coming OpenCores newsletters. If you have any questions about how we can support in development projects, do not hesitate to contact us:, +46 8 24 84 04

Article written by ORSoC in cooperation with Invensys, ORSoC

Update from OC-Team

This topic gives you an update of what has been "cooking" at the OpenCores community during the last month.

This month activities:

Website information:

  • Mail issue

Server information:

  • No issues

Our message to the community:

  • Help us improve the community, please provide feedback

Marcus Erlandsson, ORSoC

New IP-cores

Here you will see interesting new projects that have reached the first stage of development.

MESI Coherency InterSection Controller

The MESI InterSection Controller (ISC) is a coherence system controller. It supports the MESI coherence protocol for a cache data consistency. It synchronizes the memory requests of the system masters. It enables to keep the consistency of the data in the memory and in the local caches. This project provides the following elements:

1. A synthesizable controller core with a complete environment of verification, synthesis, and documentation.
2. Instructions for integrating MESI_ISC to a system.
3. A definition and requirements of the system masters.

Project status:
- Documentation: On progress. Main chapters have written.
- RTL: Done.
- Verification: On progress. A basic test plan has done.
- Synthesis: On progress. Initial synthesis on Quartus II has passed successfully.

Development status: Alpha
License: LGPL
Jan 18, 2013: Update overview description
Jan 3, 2013: Source files and verification environment were uploaded
Jan 3, 2013: New project:: MESI_ICS - MESI InterSection Controller is a cache coherence system controller.

PCI card with Xilinx X3CS500E
The card is a PCI card. Tested in 2 different PC(1 old intel and 1 recent AMD FX 64bits) , with 2 different PCI core (Raggedstone and mini-pci). The card connect 50 PCI signals and can theorically handle all feature of the PCI bus (bus master, interrupts etc). The FPGA used XC3S500E is very large and the PCI core currently use 2% of LUT space. The card is basically designed from the Raggedstone V1 design from Enterpoint LTD (same bus switch, roughly same PCI connections). The PCB is professionnaly manufactured , but the card is soldered by my hands. 3 units are currently assembled. They is spare PCB available for anyone interested.All the electronic components are available from Digikey or Mouser except for the Xilinx FPGA.

Development status: Beta
License: LGPL
Jan 10, 2013: grammatical corrections
Jan 8, 2013: spelling and grammar
Jan 8, 2013: ucf pins location
Jan 8, 2013: Added some images
Jan 8, 2013: added description

RapidIO IP library
This project contains a collection of IP cores that can be used to build RapidIO 2.2 capable devices, for example an end point, a switch or a switch with internal endpoints. All IP cores was initially developed in an internal project at Bombardier that agreed to release it to the general public.

Below are brief descriptions of the existing IP cores that are currently available and some that will be available in a near future.

This IP core implements RapidIO packet switching between a configurable number of ports. It can receive and process maintenance packets to do basic switch configuration.
Status: Available

This IP core implements a RapidIO packet queue. It can store a configurable number of packets in a configurable sized memory.
Status: Available

This IP core implements RapidIO LP-serial Physical Specification, but only the transmission independent protcol parts. This allows the development of custom PCS layers that does not follow the standard and that can use an existing legacy communication infrastructure.
Status: Available

This IP core implements a PCS (Physical Coding Sublayer) that uses an 8-bit UART as its transmission channel. It can be used by the RioSerial IP module to send RapidIO packets over a standard 8-bit, no parity, 1 stop bit, UART. It has some similarities to PPP.
Status: Will be posted soon.

This IP core implements a bridge between a RapidIO network and a Wishbone bus. It acts as a RapidIO slave endpoint and accepts NWRITE and NREAD packets that are converted into Wishbone accesses. It can be attached to a RioPacketBuffer IP module which in turn is connected either interfacing a RioSwitch (switch with local end point) or interfacing RioSerial (stand alone end point).
Status: Will be posted soon.

This IP core implements a PCS (Physical Coding Sublayer) that uses an ethernet PHY as its transmission channel. It can be used by the RioSerial IP module to send RapidIO packets over a standard ethernet cable.
tatus: Under development.

This IP core implements a bridge between an ethernet network and a RapidIO network. It emulates an ethernet PHY with an RGMII interface to make it directly attachable to a processor with an internal ethernet MAC. A RapidIO packet is encapsulated in an ethernet packet with a special ethernet type. It can be attached to a RioPacketBuffer and a RioSwitch or RioSerial depending on the specific need.
Status: Under development.


This C-code contains an implementation of RapidIO LP-serial Physical Specification, but only the transmission independent protocol parts. The C-code is written without using any OS-libraries and can be integrated into any microcontroller. It requires a custom symbol codec between the transmission channel and the lower parts of the C-stack implementation. It also requires an upper-half to interface a user application or an operating system. It has been successfully integrated into a Linux device driver and a small micro controller running FreeRTOS. It has two compiling options, non-transparent and transparent. The non-transparent answers received maintenance request packets automatically and is inteded for a normal end point implementation. If the transparent option is used, all maintenance requests are passed to upper parts of the stack. This makes it possible to, for example, simulate a switch or to emulate a full RapidIO network in software.
Status: Will be posted soon.

This C-code contains an implementation of a symbol codec that can handle a data stream generated by the IP core RioPcsUart. It is provided as an example and needs to be integrated into a custom codec suitable for the target processor.
Status: Will be posted soon.

Development status: Beta
License: LGPL
Jan 10, 2013 Updating project description with the currently available IP cores and with information about cores that will be released in a near future..
Jan 10, 2013 Adding RapidIO core implementing the channel independent parts of the LP-serial physical layer specification.
Jan 9, 2013 Adding RapidIO packet buffering IP core component, RioPacketBuffer and its testbench. It implements a packet FIFO used to store in- and outbound packets.
Jan 9, 2013 Adding the first IP core component, RioSwitch and its testbench. It implements packet switching between ports.
Jan 8, 2013 Updating project description.


Two wire RS232 communication module capable of 5, 6, 7, 8 bit word communication, Parity bit, Parity bit Polarity, 1 and 2 stop bits. Integrated with transmit and receive buffer controlled through a WishBone interface. Besides the WishBone interface auxiliary signals are provided for Buffer status and can be used for interrupt driven routines.

Development status: Planning
License: LGPL
Jan 14, 2013 Project description

Fade - Light L3 Ethernet protocol for transmission of data from FPGA to embedded PC
This project implements the simple and light protocol for transmission of data from low resources FPGA connected to the Ethernet MAC and an embedded system running Linux OS. The main goal was to assure the reliable transmission over unreliable Ethernet link without need to buffer significant amount of data in the FPGA. This created a need to obtain possibly early acknowledgment of received packets from the embedded system, and therefore the protocol had to be implemented in layer 3.

Development status: Beta
License: Others
Dec 14, 2012: Updated description of the project
Dec 14, 2012: updated status of the project

This code implements a Reed Solomon encoder/decoder for both the parity size of 8 and the 16. The Reed Solomon encoder structure implemented here is the one used in ADSL G.9956 but it is also used in lot of the other emerging communication systems such as wireless 3rd generation 3GPP standard (Wideband CDMA) and powerline communication standards like Homeplug.

Development status: Stable
License: LGPL
Nov 29, 2012: updated description of project
Nov 29, 2012: Initial release

Ethernet 10GE Low Latency MAC
This is a fork of the xge_mac and was released by the Computer Architecture Group ( of the University of Heidelberg.

Main changes in this fork:
-Unwanted FIFOs removed
-Latency reduced due to the removal of the FIFOs and a new CRC implementation
-Interface very similar to the one of the Xilinx MAC

Development status: Stable
License: LGPL
Dec 1, 2012: Code updated

FORTH processor with Java compiler
A 32-bit FORTH processor conforming to the DPANS'94. This processor was developed as diploma thesis to obtain the academic degree Diplomingenieur (Master of Computer Science) at Johannes Kepler University in Linz, Austria.

- Pipelined (6-stage) instruction execution.
- 2 stacks instead of register array.
- memory common to data and instructions.
- optional 64-bit multiplier and divider.
- optional multicore possible
- ANSI 754 floating point arithmetic.
- Hardware is Little-Endian.
- an Interruptcontroller.
- an UART.
- board specific DDR2 memory controller
- a ROM containig the BIOS, sources included
- Vendor-independent code.
- A clean, modular design.

The projects are realized on Xilinx Spartan 3A Starter board, but can be moved to other Xilinx boards.

The following software is included:
A Java-client for communication between board and user. The client includes a FORTH-Assembler and a Java compiler. The sources are included.

Development status: Stable
License: LGPL
Oct 31, 2012: corrected category
Oct 30, 2012: start

Lightweight 8051 compatible CPU
Yet another free 8051 FPGA core.
This is a 6-clocker-equivalent implementation of the MCS51 architecture, aiming at area performance.
A full description of the core features can be found in the datasheet.
The project is still immature for actual use. A comprehensive test bench has yet to be developed, for starters.

Development status: Beta
License: LGPL
Nov 27, 2012 Simplified front page text.
Nov 27, 2012 Fixed absolute path in Quartus-2 project file.
Nov 24, 2012 Tidying up the front page.
Nov 24, 2012 Updated synthesis results on Spartan-3A.
Nov 24, 2012 Added bug report notice for XCODE BRAM synthesis in XST.
Nov 23, 2012 Added 'FPGA proven' attribute to the core description.
Nov 23, 2012 Updated perfoemance data for Spartan-3.
Nov 23, 2012 Added synthesis results for Spartan-3 chips.
Nov 23, 2012 Minor fix to front page text.
Nov 23, 2012 Completion of first version of front page.
Nov 23, 2012 Added some basic information to the project front page.
Nov 23, 2012 First draft of front page. No sources committed yet.

Johan Rilegård, ORSoC

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