Newsletter March 2013
"OpenRISC inside" - Commercial product based on the OpenRISC processor
geoPebble: system for collecting seismic reflection data in glacier without cables
A few simple constraints: No cables. No connectors. Small. Ten days of run time. Same sensitivity, dynamic range, and noise that we are used to.
In other words, impossible.
Tell engineers that something is impossible, and they view it as a challenge.
Indeed, we have developed a wirelessly-connected seismic recording network called geoPebbleTM
How thick is the ice beneath your feet? How deep is the water beneath that floating iceberg in the picture
How can you work around the crevasses in the picture below?
If you are a skier, you only care if it is at least a meter or two thick and that there are no crevasses! But if you are a glaciologist (yes, there are people who care about glaciers and spend their whole lives studying them — we are glaciologists), then the size, shape, and flow speed of glaciers is a critically important measurement.
The main reason we want to measure glaciers (and ice sheets—the large ice masses of Antarctica and Greenland) is to provide better inputs to numerical models that are trying to predict future glacier volume. And because glaciers will control, to large extent, global sea-level, this matters to millions of people around the world.
One way to measure properties of the interior of the earth (glaciers, rocks, sediments beneath the sea floor, etc.) is to make a sound on the surface of the earth, and then “listen” for an echo from deep inside the earth. This is called reflection seismic imaging. It is a common technique but we have put a new spin on it with the help of our friends at Orsoc and their expertise with FPGAs.
The “listening” device is called a geophone and, traditionally, the analog output of each of many geophones is connected to a long multiconductor cable laid out on the snow. The multichannel recorder at the end of the kilometer-long cable is where the data are digitized and stored. For a nice example of the method, see the blog [FOOTNOTE 1]. The main drawbacks of this method are the management of the cable and the geometric constraint driven by the fact that the cable is easiest to lay out in a long straight line.
I have worked in Antarctica and Greenland for nearly 30 years and finally got so sick of coiling those cables and having connectors break and the snow that collects in crevices and the geophone cables getting caught in everything and... and...and… that I decided to partner with electrical engineers at our university and with Orsoc to design and build the seismic acquisition device of my dreams. I gave the engineers a few simple constraints: No cables. No connectors. Small. Ten days of run time. Same sensitivity, dynamic range, and noise that I am used to. In other words, impossible.
Tell engineers that something is impossible, and they view it as a challenge. Indeed, we have developed a wirelessly-connected seismic recording network called geoPebbleTM.
The main features of this system are that the data are digitized at the geophones and, using a custom very low power FPGA board our colleagues at Orsoc have developed for us, the data are both stored at each node and transmitted over a WiFi link to a base station. The FPGA includes a Linux system that can process and store the data using high-level programming so that our students at The Pennsylvania State University can work on the programming. They can modify and improve the performance of the system because of the relatively low barrier to entry of a standard Linux system rather than a bare-metal microcontroller system. The advantage of working with Orsoc is that the hard real-time aspects of the problem are handled in the FPGA and the lowspeed work and the filesystem, etc. are done in the Linux system.
We have had to solve a number of problems along the way, such as accurate timing (we are using a precision GPS-disciplined oscillator that we developed) and position (we are using the phase measurements of GPS to achieve decimeter accuracy in post processing). The WiFi network transmits the data in real time, but if the data are not received at the base station, they are always available on the storage within the geoPebble.
Finally, we have a unique charging mechanism: an inductive coil charging system that can transmit 15 W across the base of the geoPebble case when it is sitting on a charging mat.
With the three-component geophone inside the case; with the battery inside the case; with the charging being wireless; with the data downloaded wirelessly: I think I have achieved my dream seismic system! The full network is being built this summer for testing in Antarctica later this year. After testing, they will be available to be borrowed for scientific research and possibly for commercial applications down the road.
Orsoc has been responsible for the development of the main controller board, providing FPGA design, PCB design and Software design. The product is based on the OpenRISC platform designed by ORSoC and the a new SO-DIMM PCB board with small form factor.
Information from ORSoC about OpenRISC based products:
This is another good example of how design based on IPs from OpenCores is being used in commercial products. The last couple of years ORSoC have been responsible for many projects where we handle most of the development for our customers’ products. We are very pleased that our customers appreciate our design expertise and huge experience from designs based on IPs from OpenCores. We are also running some long time support projects. We will try to present as many of these projects a possible in the coming OpenCores newsletters. If you have any questions about how we can support in development projects, do not hesitate to contact us: email@example.com, +46 8 24 84 04
Article written by Sridhar Anandakrishnan (the glaciologist) and Sven Bilén (lead engineer) at The Pennsylvania State University, in cooperation with ORSoC
ORSoC promoting Open Source and OpenCores at the Embedded world 2013.
25th to 28th of February the yearly Embedded world trade fair and conference was hold in Nuremberg, Germany. It was a great deal of exhibitors showing new products, systems, tools, etc. Many of them promoting that they use and/or offer open source based technologies.
ORSoC got a request to do a 45 min key note speech for the conference program. It was presented by Marcus Erlandsson (CTO ORSoC) who spook about open source technology for hardware and the increasing use of FPGA in many different products.
When discussing open source technologies and OpenCores with different people/companies you always get a high interest. More and more companies start using open source alternatives and are very interested to know about available platforms/tools etc.
Being at Embedded world and Electronica is always inspiring. You meet a lot of interesting companies and interesting people. You get a feeling of what is going on in the market. Many companies do strategic investments in open source related projects and that seems to be a trend that just accelerates.
We strongly recommend you to visit these huge exhibitions within the electronic market future on.
Johan Rilegård, ORSoC
Update from OC-Team
This topic gives you an update of what has been "cooking" at the OpenCores community during the last month.
This month activities:
- No issue
- RAM replacement
Our message to the community:
- Help us improve the community, please provide feedback
Marcus Erlandsson, ORSoC
Here you will see interesting new projects that have reached the first stage of development.
Signed integer divider
A divider that calculates the quotient and remainder of a division operation in multiple clock cycles. The dividend, divisor, quotient and remainder are all 32-bit signed integers. By taking the advantage of a shifter that can shift more than one bit (up to 9 bits) during each cycle of computation, it takes less cycles to finish than a radix-2 nonrestoring divider.
Development status: Alpha
Mar 8, 2013: add description
Mar 8, 2013: add description
Spartan 6 PCIexpress card
I have designed and built a PCI express extension card with Spartan 6 FPGA. I was very attracted in testing Microprocessor cores in FPGA and also PC extension cards. So i needed a board with RAM, non volatile memory (SDHC memory cards) and FPGA.
When i saw the selling price of this kind of cards, i decided to build mine. Also it was a good exercise to conduct the fabrication of this card from schematic and PCB up to assembling.
Many features where new to me:
-High speed differential pair
-Length matching and resistor terminations for DDR3
-big FPGA chips (DDR3 and FPGA)
So i have read carefully the design recommendation from the Manufacturers (Xilinx for FPGA and Micron for the DDR3). I got documented also on the Freescale IMX35 processor reference design . All recommended to carefully control PCB impedance , differential pair length matching, DDR3 signals length matching and termination resistors on high speed signals.
I had a new tool for PCB design (Altium designer) that made the task a lot easy or at least possible
Development status: Beta
Mar 24, 2013 Added microblaze project source in downloads
Mar 23, 2013 orthographic corrections
Mar 23, 2013 Running Microblaze eprocessor
Mar 18, 2013 orthographic corrections
Mar 18, 2013 Credit line with this card PCB manufacturer contact
Mar 17, 2013 orthographic corrections
Mar 17, 2013 Photos
DQPSK Symbol Mapper
An attempt to implement a physical layer suitable for TETRA/APCO-25.
Development status: Planning
Mar 15, 2013 website editing
Atlas Processor Core
The Atlas processor is intended to be a general purpose processor for any kind of applications, that require minimal hardware resources while providing a maximum functionality ond processing power. The instruction set was inspired by the ARM and AVR ISAs. A simple assembler program is included within the project to allow easy code generation for the processor.
- 16-bit RISC open source soft-core processor
- Small outline CPU-only implementation and complex 32-bit addressing processor implementation available
- Completely written in behavioral VHDL
- Pipelined instruction execution in 5 stages
- Single cycle execution of most instructions
- Four forwarding units to accelerate internal operand fetch
- Powerful memory access and indexing instructions
- Two different operating modes with unique register sets (8x 16-bit registers each) and privileges
- Full hardware support for emulating privileged-mode programs in unprivileged-mode
- Support for tagged system call operations (software interrupt)
- Two external interrupt request signals
- Configurable internal cache* (shared for instructions and data; fully associative)
- Configurable directly accessed address area to bypass cache (used for shared memories, IO devices, ...)*
- Interface for two external coprocessors to extend the processor's functionality
- Wishbone-compatible pipelined bus interface* supporting burst-transfers
- Assembler program to easily create and assemble application code
*) Features marked with an asterisk are only available when using the complete processor (not the CPU-only implementation)
Development status: Alpha
Mar 22, 2013 added some stuff about interrupts and exception vectors
Mar 22, 2013 block diagrams of different implementation schemes added
Mar 21, 2013 new information about the programmer's model added
Mar 21, 2013 page update
Mar 21, 2013 information update
Mar 16, 2013 synthesis for new rtl files updated - svn update will follow soon
Mar 16, 2013 minor webpage changes
Mar 15, 2013 minor page changes
Mar 15, 2013 synthesis information updated
Mar 15, 2013 webpage update
Mar 14, 2013 pages changes..
Mar 14, 2013 minor edits
Mar 14, 2013 minor webpage updates
Mar 13, 2013 project information published
Mar 13, 2013 initial page setup
Johan Rilegård, ORSoC
First Linux, then nothing
Linux is by far the most common operating system in embedded systems. It is shown by EE Times annual survey to embedded developers. Up to 50 percent of all ongoing embedded projects using Linux. Last year, the figure was 46 percent. Second most popular, at 13 percent, is the real-time operating system FreeRTOS. It uses the same license as Linux, GPL. At two percent, we find yet another GPL RTOS: eCos. Other 14 OS on EE Times list - which includes all operating systems that were less than two percent - do not use open source license.
Of all the various Linux distributions in the top list, Android is the highest with 16 percent and Ubuntu second with 13 percent. Then Debian, Red Hat, Wind River, and Angstrom. Android is the operating system that has grown most since last year - from 13 to 16 percent.
The sum of the percentages in the list is not 100 because the developers can check for all the operating systems they currently use.
Microsoft's two built-in operating system, Windows Embedded and Windows Compact, has 11 percent (10% last year) and 8 percent (9 % last year) respectively.
The biggest commercial embedded operating system on the list is Wind River VxWorks at 7 percent, down from 11 percent last year. Also Micrium uC/OS II dropped four percent and has today five percent. Other classic embedded operating systems on the list is about the same share as last year.
EE Times reports the various Linux distributions separately in its rating list, while we have merged them. Since the same project in principle, can use multiple versions of Linux is 50 percent an upper limit on the proportion of projects that use Linux.
"Proprietary" operating system remains, as usual, the largest category, this year 24 percent of all projects.
The survey is based on over 2000 respondents in North American and Europe. It is worth noting that Asia is not included in the survey.
Published by Elektroniktidningen