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NEWSLETTER MAY 2013

OpenRISC development board from ORSoC

ASIC bitcoin mining product using the OpenRISC processor


State of the art bitcoin mining products armed with 28nm ASIC chips archive amazingly 350 GHash/s.
The products using the OpenRISC processor for its internal Linux system.

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Update from OC-Team


This topic gives you an update of what has been "cooking" at the OpenCores community during the last month.

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New IP-cores at OpenCores


View a list of all interesting new projects that have reached a first stage of development.

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Altera acquire Enpirion


Altera deliver breakthrough power solutions for FPGAs with acquisition of power technology innovator Enpirion.

Read more...

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Newsletter May 2013


State of the art ASIC bitcoin mining product using the OpenRISC processor for internal Linux system.


KnCMiner are developing new, state of the art, bitcoin mining products. Their first products, named Jupiter and Saturn, will be armed with 28nm ASIC chips powering the devises up to amazingly 350 GHash/s respective 175 GHash/s.

The design implemented in the ASICs will have a unique and elegant implementation solution which will give the devices quite some extra performance comparing with other implementations done in the same technology. This will also be vital since it makes it easier to handle the heat generated by the massive performance.

ORSoC handle all the design work, due to ORSoCs expertise and long experience in exactly this area of technology.

Today there is a FPGA based prototype available. This is a perfect proof of concept regarding the functionality of the design and the ability to extremely rapidly design high performance products.

The products are sold via KnCMiner (www.kncminer.com). More detailed information about the products available at their website.

Johan Rilegård, ORSoC





Update from OC-Team

This topic gives you an update of what has been "cooking" at the OpenCores community during the last month.

This month activities:

Website information:

  • No issues

Server information:

  • No issues

Our message to the community:

  • Help us improve the community, please provide feedback

Marcus Erlandsson, ORSoC





New IP-cores

Here you will see interesting new projects that have reached the first stage of development.

AY-3-8910 compatible module in Verilog

This module is software compatible with the PSG (Programmable Sound Generator) AY-3-8910. It can be used to produce music.

Development status: Beta
License: GPL
Updates:
May 15, 2013: Project blog in Spanish: http://retronica.wordpress.com/
May 15, 2013: Metainfo updated



LPD8806 RGB LED string driver
Description

Have you ever wanted to add some color to your project? Then this might be your answer. The LPD8806 RGB LED strings are available for low cost from various sites on the internet, and they come in strips which can be cut or joined to the desired length. Since the Red/Green/Blue (RGB) LEDs on the strip are driven by a serial controller IC that is also on the strip, your project can set each LED color independently of the others.
The connections to the LED strip include 4 wires: +5V, GND, clock and data. It turns out that these LED strips will also work using +3.3V as the supply voltage!
The format of the serial data stream used to drive the LEDs is given in the comments inside the VHDL code, and it can also be found by browsing the internet. The color settings are 7-bits for each color, for a total of 2^21 combinations, over 2 million different colors.
The VHDL module in this project was recently used in a Lattice Semiconductor FPGA. However, it does not include architecture specific macros, so it should be easy to use on any given FPGA or CPLD. It is parameterized so that the user can determine how many LEDs to drive, and the desired update rate to the LED string.
The color data is provided to the module by an input data bus, using an address to select which LED and which color is being loaded.
My VHDL coding style uses the "unsigned" type instead of the "std_logic_vector" type. It is easy to translate between the two using functions in "convert_pack.vhd", or you can go through and modify the code to use std_logic_vector instead.

Status

The module is ready to simulate and synthesize.
It was used as part of a larger project... Since I'm not including the full code for the entire project, I am currently only providing the LPD8806 module code plus an example of how it is instantiated and used, but without a nice testbench.
Don't worry, the code works. Just give it a try. If you create a testbench, please send it to me and I'll post it for others to use.
NOTE:
There is an "extra" module provided in the code, which can be used to send single bytes of data to the LPD8806 string. If you want to use this module, then you'll need to provide the signals "sel_led", "bus_we" and "bus_dat_wr(7 downto 0)". Then you can send individual bytes, and see the separate green, red and blue LEDs light up individually in order as each new byte is received down the chain. However, if you don't want to do that, then just delete that part of the code.

Development status: Stble
License: LGPL
Updates:
Apr 25, 2013: I found the files in "trunk" by browsing the repository, but when I downloaded the latest version, the .tar.gz seems to be empty. This might be corrected automatically?
Apr 25, 2013: Uploaded .vhd files to SVN repository. Added note in status section about debug logic that can be deleted...
Apr 25, 2013: Provided additional note about unsigned data type vs. std_logic_vector
Apr 25, 2013: Updated Description, and Status.



Ternary (3-input) Adder

This IP core provides resource efficient ternary adders, i.e., adders with three inputs performing s = x + y + z, for the Altera and Xilinx platforms. Resource efficient means that they need exactly the same resources on modern FPGAs as two-input adders, but are slightly slower.

Development status: Stable
License: LGPL
Updates:
Apr 5, 2013: infos changes



LZRW1 Compressor Core

This IP core allows lossless data compression based on the Lempel-Ziv-Ross-Williams-1 algorithm. Its focus is on high throughput (of uncompressed data) at the expense of an somewhat lower compression ratio. One byte of uncompressed data can be processed at every second clock cycle. A software decoder (decompressor) written in java is included.
The core is fully pipelined to allow high clock speeds. 66MHz can easily be achieved on a Spartan6 FPGA. This results in a maximum compression throughput of almost 32MBytes/sec.
It uses a Wishbone compliant slave interfaces to receive uncompressed data and configuration information. A second Wishbone (master) interface is used by the included DMA unit to directly transfer the compressed data to RAM or another Wishbone slave.
The project includes a file based test bench which compresses externally generated input files. The compressed file can be verified with an included java tool. Both the VHDL and java code have been tested with an Spartan6 FPGA and several 100MB of hardware generated random data. The core occupies ~500 Spartan6 slices using 1605 FF/LUT pairs of which 44% are fully used.

Development status: Stable
License: GPL
Updates:
Apr 7, 2013: minor website update
Apr 7, 2013: Added Description




Johan Rilegård, ORSoC



Altera to Deliver Breakthrough Power Solutions for FPGAs with Acquisition of Power Technology Innovator Enpirion

http://newsroom.altera.com/press-releases/nr-altera-acquires-enpirion.htm

For people involved in the development of OpenRISC this comes as no surprise. The community has for many years been using the ORDB2 with ALTERA Cyclone IV and Enpirion EN5382.

This DC/DC converter is a truly small footprint solution. The converter comes in a small 5x4 mm QFN package. External components are only two small caps. The inductor is integrated in the QFN. The device has a 3 pin VID output voltage selection.

Michael Unnebäck, ORSoC


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