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The aim of the OpenRISC project is to create free and open source computing platforms available under the GNU (L)GPL license. The platforms aim to provide:
- a free, open source RISC architecture with DSP features
- a set of free, open source implementations of the architecture
- a complete set of free, open source software development tools, libraries, operating systems and applications
Some useful hot-links:
- Information about the OR1200 OpenRISC Processor and other sources of information
- Download source code or browse in SVN
- OpenRISC bugzilla and its documentation
- Ubuntu VirtualBox OpenRISC image - Get started easy, tools are pre-installed
This project is now fully maintained through a Wiki (the Community Portal). The old web pages are still available, but no longer maintained (should NOT be used).
Project maintainers
Details
Name: or1k
Created: Sep 25, 2001
Updated: Jan 27, 2012
SVN Updated: Feb 24, 2011
SVN: Browse
Latest version: download
Statistics: View
Other project properties
Category: Processor
Language: Verilog
Development status: Stable
Additional info:
ASIC proven, Design done, FPGA proven, Specification done
WishBone Compliant: Yes
License: LGPL
Click here for the OpenRISC project details.
Active developers are welcome as maintainer of this project. The list will be updated regularly. If you think your name should be in the list, please send an email to ocadmin@opencores.org.
- This page was last modified on 30 November 2011, at 11:55.This page has been accessed 59,436 times.Privacy policyAbout OR1KDisclaimers