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From OR1K

The aim of the OpenRISC project is to create free and open source computing platforms.

The project strives to provide:

  • a free, open source RISC architecture with DSP features
  • a set of free, open source implementations of the architecture
  • a complete set of free, open source software development tools, libraries, operating systems and applications

Some useful hot-links:

  • OR1K emulator written in Javascript, running Linux: jor1k
  • ORCONF 2013 - The project's annual conference for 2013, held in Cambridge, England on October 5th and 6th


This project is now fully maintained through a Wiki (the Community Portal). The old web pages are still available, but no longer maintained (should NOT be used).



Details

Name: or1k
Created: Sep 25, 2001
Updated: Mar 1, 2012
SVN Updated: Feb 24, 2011
SVN: Browse
Latest version: download
Statistics: View

Other project properties

Category: Processor
Language: Verilog
Development status: Stable
Additional info: ASIC proven, Design done, FPGA proven, Specification done
WishBone Compliant: Yes
License: LGPL

Click here for the OpenRISC project details.

Active developers are welcome as maintainer of this project. The list will be updated regularly. If you think your name should be in the list, please send an email to ocadmin@opencores.org.

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