OR1200 OpenRISC Processor
The OpenRISC 1200 is an implementation of OpenRISC 1000 processor family.
The OR1200 is a 32-bit scalar RISC with Harvard microarchitecture, 5 stage integer pipeline, virtual memory support (MMU) and basic DSP capabilities.
Default caches are 1-way direct-mapped 8KB data cache and 1-way direct-mapped 8KB instruction cache, each with 16-byte line size. Both caches are physically tagged. By default MMUs are implemented and they are constructed of 64-entry hash based 1-way direct-mapped data TLB and 64-entry hash based 1-way direct-mapped instruction TLB. Supplemental facilities include debug unit for real-time debugging, high resolution tick timer, programmable interrupt controller and power management support.
- Central CPU/DSP block
- IEEE 754 compliant single precision FPU
- Direct mapped data cache
- Direct mapped instruction cache
- Data MMU based on hash-based DTLB
- Instruction MMU based on hash-based ITLB
- Power management unit and power management interface
- Tick timer
- Debug unit and development interface
- Interrupt controller and interrupt interface
- Instruction and Data WISHBONE B3 compliant interfaces
The OR1200 is stable and has been implemented in various commercial ASICs and FPGA. The development is always ongoing with new features and improvements. If you would like to help with the development, please post to the OpenRISC forum or send an email to email@example.com.
The main OR1200 implementation is verified by running a range of C and assembler programs under simulation and checking for correct results. The Or1ksim architectural simulator acts as the golden reference for functional behavior.
For his MSc dissertation Waqas Ahmed applied an OVM framework to provide extensive comparison of Or1ksim with the Verilog RTL, uncovering numerous bugs in the process. His code is also available for download.
The OpenRISC 1200 platform is usually implemented with a debug unit and one of the JTAG debugging interfaces from OpenCores. This provides hardware access to registers and memory and permits external stalling and reset of the processor.
Debugging can be carried out using physical hardware (FPGA or ASIC) or under simulation.
More details can be found on the debug interface page.
When implemented in a worst-case 0.18u 6LM process it should provide over 150 dhrystone 2.1 MIPS at 150MHz and 150 DSP MAC 32x32 operations. The default OR1200 configuration is about 40k ASIC gates.
Implementation and performance statistics
Default configuration in FPGA technologies
- 15K core cells (1850 FFs, 48 block RAMs) at 25MHz on Actel ProASIC3 technology
- 4K LUTs, 7 block RAM at 60MHz on Xilinx Virtex 5 technology
ORPSoC implementation performance statics (benchmarks run within ORPmon)
- OR1200, 8KByte/4KByte I/D cache, hardware multiply/divide disabled, @20MHz on Actel ProASIC3, SDR SDRAM
- Dhrystone (120,000 runs): 17,000 Dhrystones/second
- CoreMark 1.0 : 11.954573 (0.6 CoreMark/MHz) / GCC4.5.1-or32-1.0rc1 -O2 -msoft-mul -msoft-div -msoft-float / STACK
OR1200, 8KByte/4KByte I/D cache, hardware multiply/divide enabled, @20MHz on Actel ProASIC3, SDR SDRAM
- Dhrystone (120,000 runs): 20,000 Dhrystones/second
- CoreMark 1.0 : 25.773196 (1.25 CoreMark/MHz) / GCC4.5.1-or32-1.0rc1 -O2 -mhard-mul -mhard-div -msoft-float / STACK
OR1200, 32KByte/32KByte I/D cache, hardware multiply/divide enabled, @50MHz on Xilinx ML501
- Dhrystone (500,000 runs): 50,000 Dhrystones/second
- CoreMark 1.0 : 66.788100 (1.34 CoreMark/MHz) / GCC4.5.1-or32-1.0rc1 -O3 -mhard-mul -mhard-div -msoft-float -nostdlib / STACK
Minimal configuration in FPGA technologies
- 7K core cells (1100 FFs, 4 block RAMs) at 35MHz on Actel ProASIC3 technology
- 2.4K LUTs, 1 block RAM at 125MHz on Xilinx Virtex 5 technology