OpenCores

OR1200 OpenRISC Processor

From OR1K

Contents

Overview

Or1200 blocks.png


General Microarchitecture

  • Central CPU/DSP block
  • IEEE 754 compliant single precision FPU
  • Direct mapped data cache
  • Direct mapped instruction cache
  • Data MMU based on hash-based DTLB
  • Instruction MMU based on hash-based ITLB
  • Power management unit and power management interface
  • Tick timer
  • Debug unit and development interface
  • Interrupt controller and interrupt interface
  • Instruction and Data WISHBONE B3 compliant interfaces

Status

The OR1200 is stable and has been implemented in various commercial ASICs and FPGA. The development is always ongoing with new features and improvements. If you would like to help with the development, please post to the OpenRISC forum or send an email to openrisc_team@opencores.org.

Implementation information

When implemented in a worst-case 0.18u 6LM process it should provide over 150 dhrystone 2.1 MIPS at 150MHz and 150 DSP MAC 32x32 operations. The default OR1200 configuration is about 40k ASIC gates.

Implementation and performance statistics

Default configuration in FPGA technologies

  • 15K core cells (1850 FFs, 48 block RAMs) at 25MHz on Actel ProASIC3 technology
  • 4K LUTs, 7 block RAM at 60MHz on Xilinx Virtex 5 technology

ORPSoC implementation performance statics (benchmarks run within ORPmon)

OR1200, 8KByte/4KByte I/D cache, hardware multiply/divide disabled, @20MHz on Actel ProASIC3, SDR SDRAM
  • Dhrystone (120,000 runs): 17,000 Dhrystones/second
  • CoreMark 1.0 : 11.954573 (0.6 CoreMark/MHz) / GCC4.5.1-or32-1.0rc1 -O2 -msoft-mul -msoft-div -msoft-float / STACK

OR1200, 8KByte/4KByte I/D cache, hardware multiply/divide enabled, @20MHz on Actel ProASIC3, SDR SDRAM

  • Dhrystone (120,000 runs): 20,000 Dhrystones/second
  • CoreMark 1.0 : 25.773196 (1.25 CoreMark/MHz) / GCC4.5.1-or32-1.0rc1 -O2 -mhard-mul -mhard-div -msoft-float / STACK

OR1200, 32KByte/32KByte I/D cache, hardware multiply/divide enabled, @50MHz on Xilinx ML501

  • Dhrystone (500,000 runs): 50,000 Dhrystones/second
  • CoreMark 1.0 : 66.788100 (1.34 CoreMark/MHz) / GCC4.5.1-or32-1.0rc1 -O3 -mhard-mul -mhard-div -msoft-float -nostdlib / STACK

Minimal configuration in FPGA technologies

  • 7K core cells (1100 FFs, 4 block RAMs) at 35MHz on Actel ProASIC3 technology
  • 2.4K LUTs, 1 block RAM at 125MHz on Xilinx Virtex 5 technology
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