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OR1K:Community portal

From OR1K

The aim of the OpenRISC project is to create free and open source computing platforms available under the GNU (L)GPL license. The platforms aim to provide:

  • a free, open source RISC architecture with DSP features
  • a set of free, open source implementations of the architecture
  • a complete set of free, open source software development tools, libraries, operating systems and applications

Some useful hot-links:

Contents

Overview of the OpenRISC 1000 project

The OpenRISC 1000 architecture is the first set of specifications for a family of 32- and 64-bit RISC/DSP processors. Its open and modular architecture allows a spectrum of chip and system implementations at a variety of price/performance points for a range of applications. Designed with emphasis on performance, simplicity, low power consumption, scalability and versatile implementation, it targets medium and high performance networking, portable, embedded, and automotive applications.

Architecture specification

The latest draft of the architecture specification can be downloaded here (ODT format)

More information can be found on the Architecture Specification page.

Licensing

The architecture specifications are published under theGNU General Public License (GPL). The reference implementations in Verilog on this website are licensed under theGNU Lesser General Public License (LGPL). The reference toolchain and operating systems are published under the license of the upstream software, which is typically the GPL, but also other open source licenses, such as the Berkeley Software Distribution (BSD) license.

Third parties are free to create their own proprietary processor implementations. It is also possible to port proprietary software to the OpenRISC platform. Use and development of the implementations and software provided by the project is encouraged.

OR1200 processor implementation

The OpenRISC 1200 is an implementation of OpenRISC 1000 processor family.

The OR1200 is a 32-bit scalar RISC with Harvard microarchitecture, 5 stage integer pipeline, virtual memory support (MMU) and basic DSP capabilities.

Default caches are 1-way direct-mapped 8KB data cache and 1-way direct-mapped 8KB instruction cache, each with 16-byte line size. Both caches are physically tagged. By default MMUs are implemented and they are constructed of 64-entry hash based 1-way direct-mpped data TLB and 64-entry hash based 1-way direct-mapped instruction TLB. Supplemental facilities include debug unit for real-time debugging, high resolution tick timer, programmable interrupt controller and power management support.

Verification

The main OR1200 implementation is verified by running a range of C and assembler programs under simulation and checking for correct results. The Or1ksim architectural simulator acts as the golden reference for functional behavior.

For his MSc dissertation Waqas Ahmed applied an OVM framework to provide extensive comparison of Or1ksim with the Verilog RTL, uncovering numerous bugs in the process. His code is also available for download.

Debug interface

The OpenRISC 1200 platform is usually implemented with a debug unit and one of the JTAG debugging interfaces from OpenCores. This provides hardware access to registers and memory and permits external stalling and reset of the processor.

Debugging can be carried out using physical hardware (FPGA or ASIC) or under simulation.

More details can be found on the debug interface page.

SoCs based on OpenRISC

ORPSoC

ORPSoC (OpenRISC Reference Platform System on Chip) is an OpenRISC-based reference SoC. It consists of a test bench for OpenRISC processor RTL and a set of push-button builds for various FPGA development boards.

It is intended as a project that will demonstrate and test an OpenRISC-based system in simulation, as well as provide ready-made board builds to simplify bringing up an OpenRISC-based system on hardware.

ORPSoC has been ported to a number of FPGA development boards. There are pre-built images for some boards available for download.

The latest version is ORPSoCv3.

MinSoC

MinSoC, the Minimal OpenRISC System on Chip has been developed by Raul Fajardo based on the OpenRISC 1200.

Simulation models

OpenRISC can be simulated at a number of levels of abstraction

  • Or1ksim is an OpenRISC 1000 architectural simulator, providing instruction level simulation of the processor and common peripherals. It also provides extensive trace and debug facilities.
  • The primary OpenRISC 1000 RTL implementation, the OR1200, is written in synthesizable Verilog and can be simulated with any standard RTL simulator.
  • Certain tools exist which can convert the Verilog RTL into other types of models. For example, Verilator can convert synthesizable Verilog into a cycle-accurate C model.

Toolchains

At present OpenRISC is supported by a 32-bit GNU toolchain offering C and C++ support with static libraries only. The toolchain is available in two variants:

The GNU toolchain includes the following packages

  • binutils, the assembler, linker and other low level utilities.
  • GCC, The GNU Compiler Collection, supporting C and C++.
  • GDB, The GNU Debugger.

Operating systems

There are several operating systems of varying size and capability that have OpenRISC 1000 architecture support to some degree.

Linux

The latest Linux kernels are ported to the OpenRISC architecture, with a short term objective to be included in the mainline Linux distribution. Due to shortcomings in the current toolchain, support is limited to statically compiled binaries. BusyBox for OpenRISC builds and works well, however, on top of the uClibc port. Development of Linux, glibc, and support for dynamic linking is currently ongoing at the OpenRISC sister site http://openrisc.net.

RTOS

Real-time operating systems ported to OpenRISC include eCos, RTEMS, uCOS-II and FreeRTOS.

Bootloaders

ORPmon, the OpenRISC boot monitor, is a basic bootloader for OpenRISC-based systems. It supports TFTP boot and booting from SD card media.

U-Boot, the universal bootloader, is also available for OpenRISC platforms.

Get source code

Ubuntu OpenRISC VirtualBox image

The purpose with the Ubuntu OpenRISC VirtualBox image is to make it SUPER easy to get started with the OpenRISC processor platform, both with hardware and software. The VirtualBox image contain the necessary tools pre-installed for both hardware and software.

Prepackaged versions

Various versions of the system compoenents are available prepackaged for download.

Repositories for latest versions

The very latest versions of both hardware and software are held in revision controlled repositories.

There are two revision control systems that are being used to store all source-code, an SVN (subversion) system and a Git system. Currently they are not mirrors of each other, and host separate parts of the project.

SVN repository

The SVN repository currently contains the following:

  • OR1200
  • ORPSoC
  • Or1ksim (OpenRISC architectural simulator)
  • GNU toolchain port source
  • Newlib library port
  • RTOS ports
  • OR Debug proxy source

You can checkout the latest version of from SVN using: 

svn co http://opencores.org/ocsvn/openrisc/openrisc/trunk

Note: The checkout process may take a while. It may also fail to completely checkout the repository - performing an SVN update will make the checkout continue.

It's possible to browse the SVN repository using a web-SVN-GUI.

Git repository

The Git repository contains source code for the following blocks:

  • Linux kernel port
  • uClibc port

You may obtain the latest version from Git using: 

git clone git://openrisc.net/jonas/linux
git clone git://openrisc.net/jonas/uClibc

It's possible to browse the Git repository at git.openrisc.net

Bug reporting

We have now moved to using Bugzilla for all bug and issue tracking. This is still relatively new, so please tell us of any problems via the mailing lists or IRC.

Enabling Bugzilla

Important. Before you can file a bug in Bugzilla, you must register. The mechanism to do this was changed at the start of 2012, to allow self-registration using your opencores.org email address.

At the Bugzilla main page click on "New Account" at the top. This link doesn't always show - you may see text boxes for "Username" and "Password" instead. In this case, click on [X] to the right of the password box and "New Account" will appear.

Click on "New Account" and follow the instructions, remembering you must use your OpenCores email address (username@opencores.org).

Reporting a bug

The first step is to see if anyone else has already reported the bug. Use Bugzilla's search functionality to check this. If you find the bug is already there, add your own comment and add yourself to the CC list (so you get notified when the bug is fixed).

Otherwise add a new bug. You'll need to login using your opencores email address. If your user id is fred.bloggs, you will login using fred.bloggs@opencores.org. Your password will be the same as your main OpenCores password.

Note: This catches everyone out. The login is your opencores email address, not your opencores user id.

The product is "OpenRISC" and you should select the component to which the bug applies.

The severity needs some explanation:

  • blocker. This bug stops other components working
  • critical. This bug stops this component working
  • major. This bug stops this component working, but there is a workaround
  • normal. Most bugs!
  • minor. Would be nice to fix, but you can live with this bug.
  • trivial. Yes it's a bug, but there is no real need to fix it.
  • enhancement. Nothing's broken, but this would make the product better.

Leave the priority field untouched (Normal). It is for the bug fixer to prioritize his or her work.

Then add a comment explaining how to reproduce this bug. If you have a fix, then please post that as well.

Bug work flow

The standard Bugzilla work flow (diagram from the Bugzilla user guide) is as follows:

BzLifecycle.png

In large projects, each resolution requires separate verification. However, because OpenRISC is still quite a small project, that QA function may be carried out by the developer themself. However that is something we want to change as soon as the project is large enough.

The old bugtracker

The old OpenRISC bugtracker system is still online, but only as a historical record. It is no longer possible to enter new bugs into it. All the open bugs have been transferred to Bugzilla.

Guide for developers

We're still working on this. Feel free to update, or add to the discussion.

Contributor guidelines

We ask those who wish to contribute to any part of the project to check out the contributor guidelines page. These outline the general contribution practices for the OpenRISC project and any specific preferences of individual parts fo the project.

Project maintainers

Central to development are the Project maintainers who are ultimately responsible for the quality of development.

Design guidelines

SVN based hardware design

Section to be written.

SVN based software tools

All these tools (Or1ksim, GNU tool chain, newlib, various RTOS) are built using autotools (autoconf, automake and libtool). We follow the GNU practice of adding the generated autotools files to SVN.

A number of our developers use older operating systems (e.g. RHEL4), and all autotools scripts should be capable of using the following versions:

  • autoconf 1.59
  • automake 1.9.2
  • libtool 1.5.6

Steps to take before committing to SVN:

  • All components must have their ChangeLog's updated. For the GNU tools, there are OpenRISC specific ChangeLogs, named ChangeLog.or32, to avoid poluting the FSF ChangeLogs.

GIT based software tools

Section to be written.

Future work

We have a list of projects, some of which are currently in progress, and some of which we want others to start work on.

Future toolchain development

The GNU toolchain page includes a wishlist of improvements we would really like.

It is possible also that we may develop an LLVM back end if there is sufficient interest.

Match specification to implementation

The objective is to bring OR1200 specification document into line with what is actually in the RTL. A few sections still need going over (debug interface, for one.)

This task is being handled by Yann Vernier yann@orsoc.se.

Add multiple associativity to cache and MMU

This is being led by Michael Unneback (michael@orsoc.se).

Additional board implementations

This is a never ending work. Right now there are several individuals working with this task:

We welcome more participants.

Improve ORPSoC

ORPSoC contains private copies of all IP cores used and there is currently more work than should be needed to create new ports. The discussion of an improved ORPSoC aims for a design that will be more modular, extendable and easier to configure.

Wishlist

This is what we would like to develop/see developed but presently nobody is working on these projects. If you want to help, send an email to openrisc_team@opencores.org.

  • Improve OR1200 implementation
    • Identify portions of the design which are inefficient area-wise and optimise them
    • Remove all implementation-specific Verilog `defines and replace with parameters
    • Identify/isolate and find solution to critical path between fetch stage, caches and IMMU
  • Improve verification of OR1K implementations
    • Unify test code of or1ksim and ORPSoC
    • Extend test code base
    • Develop automated scripts to run GNU GCC regression suite against Verilated ORPSoC design and or1ksim
  • Identify architectural improvements
    • Registers for improved version tracking
    • Possible ISA extensions
    • Instruction class restructure
  • Even more ORPSoC board implementations.
  • Further development of the toolchain

Further information

News

11-April-2011 OpenRISC newlib toolchain 1.0rc1 released.
31-March-2011 New OR1200 tests added to ORPSoC further validating exception handling behavior.
17-March-2011 ORPSoC OR1200 Update - adding extra instruction support, implementing range exception for overflow support. ALU comparisons improved.

An archive of older news items is also maintained.

Manuals

The definitive description is the OpenRISC 1000 architecture manual, the latest version of which is maintained in SVN. A Japanese version by Takashi Okawa is also available.

Tutorials

This tutorial section contains guides and information that helps new OpenRISC users to get started more easily.

Material for beginners to soft cores on FPGA:

Guides to the toolchain:

SystemC interfaces:

Tutorials on how to implement OR1200 on Altera FPGA and Xilinx FPGA. Credits go to Resarch Group Digital Techniques, Hogeschool voor Wetenschap & Kunst, Campus de Nayer

Tutorials on how to implement OR1200 on Xilinx Spartan-6 FPGA.

  • OpenRISC implemented on the Digilent Atlys board [1]

Tutorials on how to implement OR1200 on Xilinx and Altera FPGAs using MinSoC.

  • MinSoC Tutorials [2]

Tutorials on compiling and running software in or1ksim:

FAQ

In the FAQ you can see all commonly asked questions. Feel free to add more. This FAQ focus on the OpenRISC project.

Mailing lists

There are three flavours of mailing list to support the OpenRISC project.

  1. There is the web based OpenRISC forum by OpenCores.org, which has been running since 2008.
  2. There are mailman mailing lists run by openrisc.net, particularly targeted at Linux for OpenRISC, which have been running since April/May 2011.
  3. There are mailman mailing lists run by by OpenCores, for OpenRISC and WishBone, which have been running since June 2011.

The mailing lists are relatively new (first half of 2011). However a pattern of usage seems to be emerging, where general users ask their questions on the OpenRISC forum, while developers discuss new design ideas and post patches on the two OpenRISC mailing lists.

It is recognized that having two versions of the OpenRISC mailing list (in addition to the Forum) is a problem. Efforts are under way to try to merge into a single list (not just a technical problem). In the meantime, contrary to normal advice, users are encouraged to cross-post to ensure subjects are not missed.

OpenRISC forum

The OpenRISC forum is maintained on the opencores.org website, and is a web based discussion forum. Users can use full HTML to format their messages, and all messages are help in a simple archive online. You can ask to receive notifications of new messages, by going to "My Account" (top left of this page, beneath the OpenCores logo) and selecting "OpenRISC" under the Subscriptions section. Note. This will also add you to the opencores.org OpenRISC mailing list.

A number of other forums address other OpenCores projects (the Ethernet MAC, PCI, USB etc).

Mailing lists on openrisc.net

Two are mailing lists are provided by openrisc.net. These tend to carry more technical discussion by developers and would-be developers than the forum.

  1. The Linux mailing list is for discussion of the port of Linux to OpenRISC. Monthly archives are maintained, which can be browsed by name, subject, date or thread.
  1. The OpenRISC mailing list is for general discussion of the OpenRISC architecture. Monthly archives are maintained, which can be browsed by name, subject, date or thread.

Note in particular the overlap of the second list with the OpenRISC mailing list on opencores.org. Users are particularly encouraged to cross-post until the lists can be merged.

Mailing lists on opencores.org

Two by mailing lists are provided by opencores.org. These tend to carry more technical discussion by developers and would-be developers than the forum.

  1. The OpenRISC mailing list is for general discussion of the OpenRISC archtiecture. Monthly archives are maintained, which can be browsed by name, subject, date or thread.
  1. The WishBone mailing list is for discussion of the WishBone bus architecture. Monthly archives are maintained, which can be browsed by name, subject, date or thread.

Note in particular the overlap of the first list with the OpenRISC mailing list on openrisc.net. Users are particularly encouraged to cross-post until these lists can be merged.

If you subscribe to the OpenRISC forum, you will be automatically subscribed to the OpenRISC mailing list as well.

IRC

Most of the regular contributors can be found on channel #opencores at freenode.net. They are a friendly bunch, and a good source of advice.

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