The aim of the OpenRISC project is to create free and open source computing platforms.
It aims to provide:
- a free, open source RISC architecture with DSP features
- a set of free, open source implementations of the architecture
- a complete set of free, open source software development tools, libraries, operating systems and applications
Overview of the OpenRISC 1000 project
The OpenRISC 1000 architecture is the first set of specifications for a family of 32- and 64-bit RISC/DSP processors. Its open and modular architecture allows a spectrum of chip and system implementations at a variety of price/performance points for a range of applications. Designed with emphasis on performance, simplicity, low power consumption, scalability and versatile implementation, it targets medium and high performance networking, portable, embedded, and automotive applications.
The latest version of the architecture specification can be downloadedhere
More information can be found on the Architecture Specification page.
The architecture specifications are published under theGNU General Public License (GPL). The reference implementations in Verilog on this website are licensed under theGNU Lesser General Public License (LGPL). The reference toolchain and operating systems are published under the license of the upstream software, which is typically the GPL, but also other open source licenses, such as the Berkeley Software Distribution (BSD) license.
Third parties are free to create their own proprietary processor implementations. It is also possible to port proprietary software to the OpenRISC platform. Use and development of the implementations and software provided by the project is encouraged.
There are several OR1k-compliant processor implementations available. They exist both in the form of RTL implementations that can be synthesized for FPGA/ASIC, and as software models that can run programs compiled for the OpenRISC architecture in a simulated software environment.
See the OR1K CPU Cores page for more details on these cores.
SoCs based on OpenRISC
In order to do something useful with your OpenRISC processor you need to connect it to peripheral controllers, perform system level simulations and put it in an FPGA or ASIC. To make this process easier there exists several tools that can help build a SoC based on the OpenRISC processor and the Wishbone bus. The two most prominent platforms for building a SoC are:
- MinSoC, (the Minimal OpenRISC System on Chip), developed by Raul Fajardo based on the OpenRISC 1200.
- ORPSoC (OpenRISC Reference Platform System on Chip), an OpenRISC-based reference SoC. It consists of a test bench for OpenRISC processor RTL and a set of push-button builds for various FPGA development boards.
In order to produce executable binaries for the OpenRISC architecture, a toolchain is needed. In addition to compiling and linking files, the toolchain can also be used for debugging and analysis of programs. Both major toolchains (GNU and LLVM) are supported by OpenRISC. The GNU toolchain is the most wide-spread and used, while LLVM is still considered experimental. More information about how to build and use the toolchains can be found here:
There are several operating systems of varying size and capability that have OpenRISC 1000 architecture support to some degree. Both Linux and several RTOS (Real Time Operating Systems) are available. See the Operating Systems page for an overview of all the supported Operating systems
Instead of directly booting an application from an on-board memory, a boot loader can be used to perform advanced tasks such as loading a program from TFTP or SD card. For this purpose several boot loaders have been ported to OpenRISC 1000.
- barebox, The U-boot replacement
- U-Boot, the universal bootloader.
ORPmon, the OpenRISC boot monitor(Deprecated)
Conferences and meetings
Meetings of project developers, maintainers and users are held regularly.
The next event is ORCONF 2014.
See the OpenRISC Project Meeting page for details.
Get source code
Ubuntu OpenRISC VirtualBox image
The purpose with the Ubuntu OpenRISC VirtualBox image is to make it SUPER easy to get started with the OpenRISC processor platform, both with hardware and software. The VirtualBox image contain the necessary tools pre-installed for both hardware and software.
NOTE: The VM image is old by now and uses the legacy (or32-) toolchain. A new VM image would be highly appreciated
Repositories for latest versions
OpenRISC is a large project with many different repositories for storing source code. Most of the repositories are found in OpenCores SVN or on Github
Most of the code you will need can be found at https://github.com/openrisc
- or1k-gcc - GCC
- or1k-src - binutils and GDB
- or1ksim - Simulator for or1k
- uClibc-or1k - uClibc
- Linux kernel port
...and many other
Instructions on building can be found here: OpenRISC GNU toolchain
OpenCores SVN repository
The SVN repository has over time become a dumping grounds for things related to OpenRISC development. In general, the development versions of most projects in this huge repository has moved somewhere else, but we will keep the files in SVN for backwards compatibility. The projects that still uses the OpenCores OpenRISC SVN repo as its main VCS are:
- Legacy (or32) GNU toolchain port source
- RTOS ports
Browse the SVN repository via the web-SVN-GUI.
Get a subversion checkout of the repository with
svn co http://opencores.org/ocsvn/openrisc/openrisc/trunk
Note: The checkout process may take a while. It may also fail to completely checkout the repository - performing an SVN update will make the checkout continue.
Important. Before you can file a bug in Bugzilla, you must register. The mechanism to do this was changed at the start of 2012, to allow self-registration using your opencores.org email address.
At the Bugzilla main page click on "New Account" at the top. This link doesn't always show - you may see text boxes for "Username" and "Password" instead. In this case, click on [X] to the right of the password box and "New Account" will appear.
Click on "New Account" and follow the instructions, remembering you must use your OpenCores email address (firstname.lastname@example.org).
Reporting a bug
The first step is to see if anyone else has already reported the bug. Use Bugzilla's search functionality to check this. If you find the bug is already there, add your own comment and add yourself to the CC list (so you get notified when the bug is fixed).
Otherwise add a new bug. You'll need to login using your opencores email address. If your user id is fred.bloggs, you will login using email@example.com. Your password will be the same as your main OpenCores password.
Note: This catches everyone out. The login is your opencores email address, not your opencores user id.
The product is "OpenRISC" and you should select the component to which the bug applies.
The severity needs some explanation:
- blocker. This bug stops other components working
- critical. This bug stops this component working
- major. This bug stops this component working, but there is a workaround
- normal. Most bugs!
- minor. Would be nice to fix, but you can live with this bug.
- trivial. Yes it's a bug, but there is no real need to fix it.
- enhancement. Nothing's broken, but this would make the product better.
Leave the priority field untouched (Normal). It is for the bug fixer to prioritize his or her work.
Then add a comment explaining how to reproduce this bug. If you have a fix, then please post that as well.
Bug work flow
The standard Bugzilla work flow (diagram from the Bugzilla user guide) is as follows:
In large projects, each resolution requires separate verification. However, because OpenRISC is still quite a small project, that QA function may be carried out by the developer themself. However that is something we want to change as soon as the project is large enough.
The old bugtracker
The old OpenRISC bugtracker system is still online, but only as a historical record. It is no longer possible to enter new bugs into it. All the open bugs have been transferred to Bugzilla.
Guide for developers
We're still working on this. Feel free to update, or add to the discussion.
We ask those who wish to contribute to any part of the project to check out the contributor guidelines page. These outline the general contribution practices for the OpenRISC project and any specific preferences of individual parts fo the project.
Central to development are the Project maintainers who are ultimately responsible for the quality of development.
We have a list of projects, wishlists, what people are working on here.
Note: This section isn't updated very much anymore. That isn't to say that there's nothing going on with the project - on the contrary, there is plenty going on. We'll figure out a better system of keeping people up to date with what is going on soon. In the meantime check out the IRC channel and mailing lists for an idea of what is going on.
|11-April-2011||OpenRISC newlib toolchain 1.0rc1 released.|
|31-March-2011||New OR1200 tests added to ORPSoC further validating exception handling behavior.|
|17-March-2011||ORPSoC OR1200 Update - adding extra instruction support, implementing range exception for overflow support. ALU comparisons improved.|
An archive of older news items is also maintained.
See the architecture specification page for the architecture manual.
A Japanese version of the OR1200 specification by Takashi Okawa is also available.
This tutorial section contains guides and information that helps new OpenRISC users to get started more easily.
Material for beginners to soft cores on FPGA:
- Sven-Åke Andersson has written a comprehensive blog on OpenRISC for newbies, which offers a guide to the complete design flow.
Guides to the toolchain:
- Jeremy Bennett. Embecosm Application Note 2. The OpenCores OpenRISC 1000 Simulator and Tool Chain: Installation Guide. Issue 3, November 2008.
- Robert Guenzel. Embecosm Application Notes 1 and 2 and MacOS 10.4
- Jeremy Bennett. Embecosm Application Note 1. Building a Loosely Timed SoC Model with OSCI TLM 2.0: A Case Study Using an Open Source ISS and Linux 2.6 Kernel. Issue 2, May 2010.
- Robert Guenzel. Embecosm Application Notes 1 and 2 and MacOS 10.4
Tutorials on how to implement OR1200 on Altera FPGA and Xilinx FPGA. Credits go to Resarch Group Digital Techniques, Hogeschool voor Wetenschap & Kunst, Campus de Nayer
- Altera HW tutorial local copy of the PDF and possibly updated version at the original site.
- Xilinx HW tutorial local copy of the PDF and possibly updated version at the original site.
Tutorials on how to implement OR1200 on Xilinx Spartan-6 FPGA.
- OpenRISC implemented on the Digilent Atlys board 
Tutorials on how to implement OR1200 on Xilinx and Altera FPGAs using MinSoC.
- MinSoC Tutorials 
Tutorials on compiling and running software in or1ksim:
- Simple C program compilation and execution from rte.se: Writing an application program
A Dynamic Reconfigurable OpenRISC Framework called Proteus : Proteus Framework
In the FAQ you can see all commonly asked questions. Feel free to add more. This FAQ focus on the OpenRISC project.
Two by mailing lists are provided by opencores.org. These tend to carry more technical discussion by developers and would-be developers than the forum.
- The OpenRISC mailing list (firstname.lastname@example.org) is for general discussion of the OpenRISC archtiecture. Monthly archives are maintained, which can be browsed by name, subject, date or thread.
- The WishBone mailing list is for discussion of the WishBone bus architecture. Monthly archives are maintained, which can be browsed by name, subject, date or thread.
If you subscribe to the OpenRISC forum, you will be automatically subscribed to the OpenRISC mailing list as well.
The OpenRISC forum is maintained on the opencores.org website, and is a web based discussion forum. Users can use full HTML to format their messages, and all messages are help in a simple archive online. You can ask to receive notifications of new messages, by going to "My Account" (top left of this page, beneath the OpenCores logo) and selecting "OpenRISC" under the Subscriptions section. Note. This will also add you to the opencores.org OpenRISC mailing list.
A number of other forums address other OpenCores projects (the Ethernet MAC, PCI, USB etc).
Most of the regular contributors can be found on channel #opencores or #openrisc at freenode.net. They are a friendly bunch, and a good source of advice.
Logs of the #openrisc channel can be found here.