OR1K CPU Cores
This page gives a summary of each of the known available OR1k-compliant implementations.
This processor has its own page on this wiki with details, see OR1200 OpenRISC Processor
It's source code can be found in the OpenCores SVN
This core aims to implement a variety of pipelines offering the ability to trade area for speed. It also is intended to be a good platform for experimentation with pipeline implementations such as superscalar, out of order execution, threading and the like.
The current three pipelines, however, are relatively simple and being developed to provide a stable, up-to-date implementation going forward. It is intended for implementation on both FPGA and ASIC.
Implemented peripherals are tick timer, PIC unit, debug unit (single stepping and software breakpoints only), caches (some pipelines only) and Wishbone bus interface.
It is currently hosted here: http://github.com/openrisc/mor1kx
It is licensed under a weak copy-left (source file level) license created specifically for it, the Open Hardware Description License (OHDL). For details see http://juliusbaxter.net/ohdl
AltOR32 is an OpenRISC 1000 architecture derived RISC CPU targeted at small FPGAs and contains only the most basic ISA features from the OpenRisc project.
Instructions & registers relating to Vector, floating-point, 64-bit extensions, MMU & Cache have been omitted.
The aim of AltOR32 is to provide a simple 32-bit soft CPU architecture aimed at control applications that can fit in low-end FPGA technology.
This architecture re-uses the OpenRisc GNU toolchain hence implements all instructions that cannot be disabled. Anything else is viewed as beyond the scope of this cut-down soft-CPU implementation.
It is hosted here on OpenCores: http://opencores.org/project,altor32
This core implements the complete OpenRISC ORBIS32 instruction set. It has a very simple design, one could say suboptimal, or even naive. It does not implement the jump delay slot. It has a single Wishbone bus for both instruction fetches and data access.
It is flagged as no longer maintained.
The or1knd i5 is written in VHDL and is part of the CARPE research project by Peter Gavin. It is a 5-stage pipeline, delay-slot-free implementation.
Find its source code at https://github.com/pgavin/carpe/tree/master/hdl
Or1ksim is the golden reference instruction set simulator (ISS) for OpenRISC 1000, providing instruction level simulation of the processor and common peripherals. It also provides extensive trace and debug facilities.
CPU ID Table
This table identifies CPU implementations (and models) as per the 8-bit CPUID field in the VR2 introduced in OR1K architecture version 1.0.
Please contact the OpenRISC developers via the mailing lists if you have an OR1k-compliant implementation and would like to be listed on this page and assigned a CPUID.