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Data_Path_Proc :: Overview

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Details

Name: 16-32_processor_datapath
Created: Aug 16, 2013
Updated: Aug 16, 2013
SVN: No files checked in

Other project properties

Category: Processor
Language: VHDL
Development status: Beta
Additional info: Design done, Specification done
WishBone Compliant: No
License: LGPL

Description

This is a VHDL code for a datapath processor that performs lots of arithmetic operations.Beside making design for ordinary blocks, we introduced the usage of IP Cores through the usage of divider IP Core. In addition to that, Floating Point Unit " ADD/SUB, Multiplier, Divider" is introduced through the usage of IP Cores dedicated for Xilinx FPGA EDA Tools.

The Architecture Contains the Following Components:
- 16 bit Data Memory.
To read the Operands of the Arithmetic Logic Unit "ALU" From it.

- 16 bit Register File.
To read the Operands of the Arithmetic Logic Unit "ALU" From it.

- 16 bit Register File based FIFO.
To write in the Output of the Arithmetic Logic Unit "ALU".

- Arithmetic Logic Unit "ALU"
To perform different Arithmetic and Logic Operations.

- Multiplexers
To choose the data input to the ALU either Immediate by the user, memory, register file, or output data from the ALU.

- Integer Divider IP Core

- Floating Point Unit IP Core "ADD/SUB + Multiplier + Divider"

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