2 way superscalar processor :: Overview

Project maintainers


Name: 2-way_superscalar_processor
Created: Nov 28, 2014
Updated: Jul 2, 2017
SVN: No files checked in

Other project properties

Category: Processor
Language: VHDL
Development status: Alpha
Additional info: Design done
WishBone compliant: No
WishBone version: n/a
License: LGPL


A simple 2 way 32-bit data handling in-order superscalar microprocessor with limited op-code and memory designed using VHDL. Its main feature is that it uses one clock and does not use any system bus to read and write data to the memory which increases the performance by decreasing the overall latency of the microprocessor.

Currently the project files is on GitHub at


This project is licensed under LGPL license, version 3.0(LGPL-3.0)

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