2 way superscalar processor :: Overview
Created: Nov 28, 2014
Updated: Dec 11, 2014
SVN: No files checked in
Other project properties
A simple 2 way 32-bit data handling in-order superscalar microprocessor with limited op-code and memory designed using VHDL. Its main feature is that it uses one clock and does not use any system bus to read and write data to the memory which increases the performance by decreasing the overall latency of the microprocessor.
Currently the project files is on GitHub at https://github.com/vishpbharadwaj/2Wss
This project is licensed under LGPL license, version 3.0(LGPL-3.0)