6502_Verilog_Design :: Overview
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Name: 6502_verilog_design
Created: May 25, 2010
Updated: Oct 31, 2010
SVN: No files checked in
Other project properties
Category: Processor
Language: Verilog
Development status: Mature
Additional info:
none
WishBone Compliant: No
License: LGPL
Description
This 6502 Project is new to Basic CPU Design(Cisc) before Risc .
I have made a design as many reference books
( I read and had reference textbooks as follows
1)Verilog HDL,
2)Digital Logic,
3)Digital System,
4)Advanced Digital Design with Verilog HDL,
5)Computer Architecture,
6)Computer Organization,
7)Microprocessors and Microcomputers,
8)컴퓨터 구조 설계,
9)고성능 마이크로프로세서 구조 및 설계 방법,
10)6502,
11)8051,
12)68000,
13)8086,
14)80386,
15)ARM etc
)
and changed 6502 internal function a little.
For example, memory controller is included in my 6502 Cisc ,
but will try to follow 6502 compatible instruction Set Architecture.
Now, I have made 44 instructions of 6502 and tested simulation and verified it.
Added Instuctions as Followed 2010-05-26
1)ADC_Imm,
2)AND_Imm,
3)EOR_Imm,
4)ORA_Imm,
5)ADC_Abs,
6)ASL_ACC,
7)LSR_A,
8)ROL_ACC,
9)ROR_ACC,
10)BCC,
11)BCS,
12)BEQ,
13)BNE,
14)BPL,
15)BVC,
16)BVS,
17)CLC,
18)CLD,
19)CLI,
20)CLV,
21)CMP_Imm,
22)CPX_Imm,
23)CPY_Imm,
24)DEC_AX,
25)DEX,
26)DEY,
27)INC_A,
28)INX,
29)INY,
30)JMP_A,
31)LDA_I,
32)LDA_A,
33)LDX_I,
34)NOP_I,
35)SED_I,
36)SEI_I,
37)STA_A,
38)STX_A,
39)TAX,
40)TAY,
41)TSX,
42)TXA,
43)TXS,
44)TYA
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2010.05.30 (implemented by today)
1)ADC Zero Page,Zero Page X,Absolute,Absolute X,Absolute Y,
2)AND Zero Page,Zero Page X,Absolute,Absolute X,Absolute Y,
3)ASL,LSR,ROL,ROR: Zero Page,Zero Page X,Absolute,Absolute X,
4)CMP Zero Page,Zero Page X,Absolute,Absolute X,Absolute Y,
5)CPX Zero Page, Absolute,
6)CPY Zero Page, Absolute,
7)DEC Zero Page,Zero Page X,Absolute,
8)INC Zero Page,Zero Page X,Absolute X,
9)JMP Indirect
10)LDA Zero Page,Zero Page X,Absolute,Absolute X,Absolute Y,
11)PHA,PHP,PLA,PLP,
12)STA Zero Page,Zero Page X,Absolute,Absolute X,Absolute Y,
13)STX Zero Page,Zero Page Y,
14)STY Zero Page,Zero Page X,
Later Soon, I will make instructions of 6502 not to be implemented and I will back here.
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