ACEX 1K50 board
Project maintainers
Details
Created: Sep 11, 2004
Updated: Dec 20, 2009
SVN Updated: Mar 10, 2009
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 0 reported / 0 solved
Other project properties
Language:
Development status:Stable
Additional info:FPGA proven
WishBone compliant: No
WishBone version: n/a
License: GPL
Description
This is a small board with the low-cost ACEX FPGA with some SRAM and Flash. It is designed as a module for soft-core CPU development. I've used this board as basis for JOP - the Java processor. JOP still fits into the ACEX 1K50.
See some pictures of the board at: http://www.jopdesign.comboard.jsp
The schematic and the PCB layout is provided under GPL.
Features
- Altera ACEX 1K50TC144-3 FPGA
- Voltage regulators (3V3, 2V5)
- Crystal clock (20 MHz)
- 512KB Flash (for FPGA configuration and program)
- 128KB Ram
- Byteblaster port
- Watchdog with LED
- EPM7032 PLD to load FPGA from flash (on watchdog reset)
- Serial interface (MAX323A)
- 56 general IO pins
Status
- Board is final
- Used in several projects
- Single page schematic can be used with the free version of Eagle: http://www.cadsoft.de
FILE: jopcore.pdf
FILE: jopcore.pdf
DESCRIPTION: Schematic
- abc