Basic DES Crypto Core :: Overview

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Name: basicdes
Created: Oct 13, 2003
Updated: Nov 6, 2010
SVN Updated: Mar 10, 2009
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Other project properties

Category: Crypto core
Language: VHDL
Development status: Stable
Additional info: none
WishBone compliant: No
WishBone version: n/a


The BasicDES Cryptography Core is a small, fast implementation of the DES-56 encryption standard. It perfoms single DES encryption and decryption functions in ECB mode, and can accept a new key for each operation without performance cost. With additional wrapper logic, CBC, CFB and Triple DES modes can also be supported.


The DES-56 cypher is a block cypher operating on 64-bit blocks. A 64-bit key is used, of which every eighth bit is ignored, giving an actual key size of 56 bits. Using a predetermined convolution pattern, 16 round keys are generated from the cypher key. In ECB mode, each block is processed without reference to the preceding or succeeding block, as follows:

- An initial data convolution swaps the bits of the message block in a specific pattern.
- 16 identical rounds of encryption processing are performed. For each round:
- The 64-bit input block is considered as two 32-bit blocks, called left and right.
- The right block is output without further processing as the left block for the next round.
- The right block is expanded from 32 to 56 bits, and exclusive-ored with the current round key.
- The resulting 56 bit string is substituted in 6-bit groups with 4-bit S-boxes, giving a 32-bit result.
- The bits of this string are swapped according to a fixed convolution pattern, and the result is exclusive-ored with the left block.
- The resulting 32-bit block is output as the right input block for the next round.

After 16 rounds have been completed, a final data convolution swaps the bits of the output block in a fixed pattern to produce the cyphertext.

Decryption is simply the encryption process with the round keys applied in reverse order.


- ECB mode encryption/decryption
- Each operation is independent. Encryption and decryption operations can be interleaved as required.
- Zero time key processing. A new key can be specified for each operation without affecting performance.
- Each 64-bit encryption or decryption operation is completed within 17 clock cycles, from rising edge of DS to rising edge of RDY.
- Maximum clock rate is approximately 179MHz.
- Maximum sustainable throughput is approximately 670 Mbps.
Device Utilization and Performance
The Virtex2 implementation of this core occupies approximately:
- 789 slices
- 1457 4-input LUT's
- 17,047 equivalent gates


- Documentation has been improved.

Perttu Fagerlund has added the following:
- Key handling has been improved by Perttu Fagerlund. The 1.2 core occupies less than half the logic cells that the 1.1 core occupied. The utilization statistics listed above are for the 1.1 version.
- Optional functionality for the RDY signal in 1.2: The rdy signal will be set low at reset. Otherwise, it behaves as in version 1.1.
- Optional signals in the interface: RDY_NEXT_CYCLE, when high, indicates that output data will be valid on the following clock. RDY_NEXT_NEXT_CYCLE, when high, indicates that output will be ready on the second following clock. These signals may be commented out or left unconnected depending on your requirements.

Note: The test bench is for the 1.1 version. It does not use the optional signals defined in the 1.2 version.

Pin Description

- RST - The reset signal is used to set all internal signals to a known state and prepare the core for operation. It should be strobed high at least once after power on and before attempting the first cryptographic operation.

- IKEY - part of the input data set, the 64-bit input cypher key must be presented with each input data block. The core expects this bus to be valid on the rising edge of the DS signal.

- IMSG0 - part of the input data set, the 64-bit input message block must be presented for each cryptographic operation. The core expects this bus to be valid on the rising edge of the DS signal.

- DECRYPT - part of the input data set, the DECRYPT signal indicates the direction of the cryptographic operation. When 0, the core expects the imsg0 bus to hold plaintext to be encrypted to cyphertext. When 1, the core expects the imsg0 bus to hold cypertext to be decrypted to plaintext. This signal must be valid on the rising edge of the DS signal.

- DS - the DS signal is the data strobe. When momentarily strobed high, it indicates the input data set is valid, and signals the core to start a cryptographic operation. Only the rising edge of this signal has meaning: all other states are ignored.

- ODATA - the 64-bit output data bus is used to export the result of the cryptographic operation from the core. This bus is guaranteed to carry valid data on the rising edge of the RDY signal.

- RDY - the RDY signal has two purposes: first, when high, it indicates that the core is idle and ready to receive input data. Second, when this signal transitions from low to high it indicates that the result of the last cryptographic operation is valid and available on the ODATA bus. The ODATA bus retains its last assigned value until the next rising edge of RDY, or until RST is asserted.

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