bus_arbiter_BIST :: Overview

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Name: bus-arbiter-with-bist-capability
Created: Jun 18, 2012
Updated: Jun 2, 2017
SVN: No files checked in

Other project properties

Category: Other
Language: VHDL
Development status: Alpha
Additional info: Design done
WishBone compliant: No
WishBone version: n/a
License: LGPL


When more than one independent processor is connected to system, that they require access to same set of system resources for ex memory.
Designed a system that accept data from each independent processor and arbitrate which one is granted access to memory at any one time.
Each independent processor will initiate a memory-required signal when it wants access to memory and will deactivate the same when the job is over. If more than one processor request for the bus at the same time , access should be granted on round robin basis.
This is in order to ensure that no one independent processor is locked out while another has continuous access. Continuous access is to be granted to any one processor for a period of time. This time period should be separately programmable from the data bus of one the period is not explicitly set, a 128 clock cycle delays should default.
The design is aimed at speed efficiency.

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