cpu65c02_tc - R65C02 Processor Soft Core with accurate timing :: Overview
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Details
Name: cpu65c02_true_cycle
Created: Apr 12, 2008
Updated: Mar 16, 2010
SVN Updated: Mar 10, 2009
SVN: Browse
Latest version: download
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Other project properties
Category: Processor
Language: VHDL
Development status: Beta
Additional info:
FPGA proven
WishBone Compliant: No
License: GPL
Description
The 65C02 by Rockwell is the upgraded version of the legendary Rockwell's R6502. cpu65c02_tc offers you an accurate timing for all new and upgraded op codes of the R65C02. This soft core was generated in VHDL, Verilog and designed with Mentor's HDL Designer.
It comes also with graphical views formatted in HTML to show and explain very clearly the hierarchy of the whole design.
Please feel free to tell me any ideas, errors or some thing else like special functions, testbenches or documentation. Use the "Tracker" link to do this.
Features
- true cycle timing for all official opcodes
- unknown op's decoded as "NOP/0xEA"
- one clock source
- input signal "rdy_i" for generating waitstates (see attached specification of R65C02)
- output signal "sync_o" to indicate an op fetch (see attached specification of R65C02)
- input signal "so_n_i" sets the internal OV Flag (see attached specification of R65C02)
- fully synthesizable VHDL and Verilog
Status
- Based on the cpu6502_tc core
- This version will support Rockwell's 65C02 (other variants are planed for future)
- Core is running in a APPLE //e SoC and tested under ProDOS V2.0.3
CORE: "READY"
LICENSE: Puplished under GPL V3
DOCUMENTATION: "on working"
TESTBENCHES: "on working"
TESTSOFTWARE: "on working"
QUALITY:
- most of the new R65C02 op codes are tested under real working conditions (APPLE //e SoC)
- irq_n_i: only simulated
- nmi_n_i: only simulated
- so_n_i: only simulated
- all other signals: simulated and approved under real working conditions (APPLE //e SoC)
History
Feb-25-2009
- Correct "RTI" (wrong: use of stack pointer)
- Correct "RMBx" & "SMBx" (wrong: bit translation)
- Rename all states of "FSM Execution Unit" for better reading
- (85%) Finish working for Specification of cpu65C02_tc
- Correct timing for addressing mode "ABS,X" for "INC" (wrong: 6 cycles instead of 7)
- Optimize end states of "STA" (s197,s207,s200,s213)
Jan-04-2009
- Deleted unused/duplicated nets, registers and modules. Renamed some blocks. Synthesis run now without warnings.
Dec-01-2008
- CVS loaded with updated finite state machine (bug fixes for interrupts)
- Include an example for specification (copied from cpu6502_tc - on working)
Aug-05-2008
- CVS loaded with BETA source files (VHDL)