DDS Signal Generator :: Overview
Created: Feb 1, 2012
Updated: Feb 4, 2012
SVN: No files checked in
Other project properties
Direct Digital Synthesis Signal Generator in VHDL tested and implemented in FPGA (Altera Cyclone 2).
I uploaded the source code files in Downloads section.
The source code file is "DDS Sourcecode.zip(rename)".
Please rename the file form .odt to .zip. (Sorry. I do not know how to use SVN. That's why i uploaded like this).
If you want all the source code files accompanying my other work related to this project, download "Source code(other files) (rename" and rename to .zip.
I also uploaded the source code in doc format. Download, Open & copy to VHDL file.