DDS Signal Generator :: Overview

Project maintainers


Name: dds_signal_generator
Created: Feb 1, 2012
Updated: Feb 4, 2012
SVN Updated: May 23, 2017
SVN: Browse
Latest version: download
Statistics: View

Other project properties

Category: Other
Language: VHDL
Development status: Stable
Additional info: Design done, FPGA proven, Specification done
WishBone Compliant: No
License: LGPL


Direct Digital Synthesis Signal Generator in VHDL tested and implemented in FPGA (Altera Cyclone 2).

Source code

I uploaded the source code files in Downloads section.
The source code file is "DDS".
Please rename the file form .odt to .zip. (Sorry. I do not know how to use SVN. That's why i uploaded like this).
If you want all the source code files accompanying my other work related to this project, download "Source code(other files) (rename" and rename to .zip.
I also uploaded the source code in doc format. Download, Open & copy to VHDL file.

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