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Educational 3 Bus Arch. Processor :: Overview

Project maintainers

Details

Name: edu_3bus_arch_processor
Created: Apr 26, 2012
Updated: May 18, 2013
SVN: No files checked in

Other project properties

Category: Processor
Language: VHDL
Development status: Mature
Additional info: Design done, Specification done
WishBone Compliant: No
License: LGPL

Description

A simple Educational 3 bus Architecture processor used as a tutorial mini-Project for Processor Controller and Instruction Set Architecture using VHDL without addressing modes for simplicity.

Features

32 Register 32bit each
16 ALU Operation
33 simple RISC ISA
do Files for each component
Testbench file Describe the Processor behavior

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