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Details

Name: ezidebug
Created: Jul 26, 2013
Updated: Jul 29, 2013
SVN Updated: Aug 15, 2013
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 0 reported / 0 solved
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Other project properties

Category:Testing / Verification
Language:C/C++
Development status:Stable
Additional info:
WishBone compliant: No
WishBone version: n/a
License: LGPL

Description

EziDebug is an easy-to-use versatile logic simulation tool for verification and debugging of digital circuits. It supports inserting scan chains in projects. Furthermore,more functions and characteristics will be opened. This manual is intended for users with no previous experience with EziDebug . It introduces you with the basic flow how to set up EziDebug. The example used in this tutorial is a small design written in Verilog and only the most basic commands will be covered in this manual. This manual was made by using Version 1.0 of EziDebug on Windows.