OpenCores

5x4Gbps CRC generator designed with standard cells :: Overview

Project maintainers

Details

Name: fast-crc
Created: Jul 22, 2002
Updated: Aug 8, 2013
SVN Updated: Mar 10, 2009
SVN: Browse
Latest version: download
Statistics: View

Other project properties

Category: Arithmetic core
Language: VHDL
Development status: Stable
Additional info: ASIC proven, Design done, Specification done
WishBone Compliant: No
License: GPL

Description

A 32-bit parallel and highly pipelined Cyclic Redundancy Code (CRC) generator is presented. The design can handle 5 different channels at an input rate of 2Gbps each (the total output throughput is 5x4Gbps.)

The generated CRCs are compatible with the 32-bit Ethernet standards. The circuit has been implemented with standard cells in a 0.35Micron standard CMOS process using the properties of Galois Fields and has been conceived as a "free" IP.

Features

- 5 independent channels @ 4Gbps each
- Works (simulations) with a standard AMS 0.35Micron process

Status

- Ready to use.

© copyright 1999-2017 OpenCores.org, equivalent to ORSoC AB, all rights reserved. OpenCores®, registered trademark.