OpenCores

filtro_FIR :: Overview

Project maintainers

Details

Name: fir_filter
Created: Mar 22, 2013
Updated: Aug 13, 2015
SVN Updated: Apr 12, 2015
SVN: Browse
Latest version: download
Statistics: View

Other project properties

Category: DSP core
Language: VHDL
Development status: Stable
Additional info: Design done, FPGA proven
WishBone compliant: No
WishBone version: n/a
License: LGPL

Description

VHDL Parametrizable FIR Filter

Implementation:

-Direct Form II
-Real format entry for normalized coeficients
-Internal fixed-point implementation (configurable resolution)

Simulation:

-Matlab file (.m)
-VHDL testbench and macro (.do) for simulation

===========================================================
EXAMPLE
===========================================================

duv_FIR_low_area : ENTITY WORK.FIR_low_area

GENERIC MAP(
..data_length...=>..12,....-- input/output length
..data_signed...=>..true,..-- input/output type (signed or unsigned)
..improv_t........=>..false,.-- minimal timing improvement (+1 cycle delay)
..bits_resol.......=>..16,....-- bits for decimal representation of coeffients
..taps..............=>..5,.....-- order+1, 2 taps (coefficients) as minimum
..coefficients....=>..(.......-- normalized coefficients (bo,b1, ..., bN)
............................-0.11735685282030676,
.............................0.23471370564061372,
.............................0.7066280917835991,
.............................0.23471370564061372,
............................-0.11735685282030676,
.............................OTHERS=>0.0)....-- (always end with "others=>0.0")

PORT MAP(
..areset.....=>..areset,..-- active high
..sreset.....=>..'0',.......-- active high
..clock_fs..=>..CLK,
..enable....=>..'1',
..xn..........=>..input,....-- FILTER INPUT (fixed-point or whole number)
..yn..........=>..output...-- FILTER OUTPUT (keeps same format as input)
);


ENJOY!!!

© copyright 1999-2017 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.