fifo to use gray pointer :: Overview

Project maintainers


Name: fito_to_use_gray_pointers
Created: Mar 30, 2013
Updated: Dec 8, 2013
SVN: No files checked in

Other project properties

Category: Memory core
Language: Verilog
Development status: Alpha
Additional info: Design done, FPGA proven
WishBone Compliant: No
License: LGPL


Fifo Design to use Gray pointer

Introduction Fist Revision Design
1) Fifo verilog design code to use read gray pointer and write gray pointer
2) Adder verilog code to use 1’s complement and 2’s complement,it is used to increment or decrement read pointer or write pointer.
3) Full Adder verilog code to add fully two 32 bits operands.
4) Bin2Gray verilog code to convert Binary Code to Gray Code.
5) Generate Full and Empty Signals.

Second Revision Design as follows (6~10)
6) Circular Queue Fifo design code to use read gray register, write gray register, data gray register.
7) Gray Counter Up/Down(or Adder/Subtractor) doesn't use complement.
8) Gray2Bin convertion module uses to calcualte data count to remain in Fifo now.
9) Full and Empty Signals use to display Fifo status.
10) Gray Counter Resouce Sharing is to reduce Gray Counter logic just one.

reference> Altera Web Site Gray Counter Verilog Source,
Verilog Designer's Library,
Advanced Digital Design with Verilog HDL,
Digital Design (mano)

Questions of my Fifo to my emails :
Thanks to all of you !!!

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