OpenCores

c - VHDL Co-Simulation with FLI

Project maintainers

Details

Name: fli
Created: Oct 4, 2013
Updated: May 26, 2017
SVN: Check description below for external links
Bugs: 1 reported / 0 solved
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Other project properties

Category:Testing / Verification
Language:VHDL
Development status:Stable
Additional info:
WishBone compliant: No
WishBone version: n/a
License: Others

Description

Using ModelSim Foreign Language Interface for c - VHDL Co-Simulation and for Simulator Control on Linux x86 Platform

Writing testbenches in VHDL can be very cumbersome. This can be solved by using a programming language with more features that does not need to bother about hardware implementation restrictions. This project demonstrates how plain c can be used for testing. Besides generating Stimuli and Analyze results, optional features, like a control interface and simulation accelerators, have been added to this testbench environment.

code can be found on
https://github.com/andrepoolfli