Configurable FPGA Architecture for Hardware-Software Merge Sorting :: Overview
Created: Jul 7, 2016
Updated: Sep 28, 2016
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A hardware-software FPGA accelerated based solution for very large data set merge sorting. The accelerator uses a FIFO based approach for sorting. The main contributions of the proposed implementation are: configurable FIFO buffers in order to address the variable size of the pre-sorted arrays in the merge sorting algorithm, and FIFO buffer size tailored for reduced memory usage of the software component. It has been implemented on Xilinx Zynq platform.