HASM TestBench Vector Generator :: Overview
Other project properties
HASM is a simple instruction simulator for use in the verification of FPGA/CPLD designs that must attach to a processor bus. HASM is meant to attach to a bus model that mimics the device attached to the FPGA or CPLD under test. HASM can be used as though it were a processor within the simulation environment without the tremendous increase in simulation times due to the overhead involved in simulating a real processor.
The HASM instruction simulator is comprised of two components: a Windows-based IDE and a VHDL module capable of reading the vector file generated by the HASM IDE. HASM 'programs' are written using assembler-like instructions. These instructions include Calls and Jumps to allow the testbench vector listing to be traversed linearly or recursively.
HASM is meant to attach to a bus-specific VHDL core. The HASM VHDL module incorporates a simple, generic bus to ease the creation of the bus-specific module. This generic bus supports single and burst-oriented accesses. In addition, the HASM core contains an interrupt line that causes the HASM core to jump to a user-defined location in the HASM source program.
Currently HASM has completed bus models for VME bus, Marvell Discovery Device Bus, Xilinx's IPIF bus, Analog Devices' ADSP-21160 Sharc bus and the 68K-based Motorola QUICC.
- Instruction-Based Testbench Vector Generator
- Includes Instructions to Alter Vector Flow:
- Call, Jump, Return
- Comparison Instructions Useful in Verification of DUT responses:
- Compare Less, Compare Greater, Compare Equal
- Single and Burst Oriented Data Transfer Instructions
- Stack Based Instructions
- Push, Pop
- Boolean Instructions
- AND, OR
- Math Instructions
- Add, Subtract
- Interrupt Support
- Single Interrupt Input to HASM Module
- .ORG Directive for Creation of a Interrupt Service Routine in Vector File
- Four General Purpose Registers
- One General Purpose Register Routed out of HASM Module to be used as GPIO
- Internal 256-word Scratch-Pad memory for Burst data Storage and Verification
- 8 bit, 16 bit, 24 bit and 32 bit Transactions Alterable by Instruction Modifiers (wr.b, wr.w, rd.b, rd.w)
- Currently Executing Instruction Visible within Simulator (allows vector file debug)