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HDLC controller :: Overview

Project maintainers

Details

Name: hdlc
Created: Sep 25, 2001
Updated: Dec 24, 2013
SVN Updated: Mar 10, 2009
SVN: Browse
Latest version: download
Statistics: View

Other project properties

Category: Communication controller
Language:
Development status: Stable
Additional info: none
WishBone compliant: Yes
WishBone version: n/a
License:

Features

- 8 bit parallel backend interface
- use external RX and TX clocks
- Start and end of frame pattern generation
- Start and end of frame pattern checking
- Idle pattern generation and detection (all ones)
- Idle pattern is assumed only after the end of a frame which is signaled by an abort signal
- Zero insertion
- Abort pattern generation and checking
- Address insertion and detection by software
- CRC generation and checking (Optional, external, since CRC-16 or CRC-32 can be used)
- FIFO buffers and synchronization (External)
- Byte aligned data (if data is not aligned to 8-bits extra random bits are inserted)
- Q.921, LAPB and LAPD compliant.
- For complete specifications refer to spec document

IMAGE: HDLC_top.jpg

FILE: HDLC_top.jpg
DESCRIPTION: Core top block diagram

Status

The VHDL code is ready in the opencores CVS. The code needs verification contact me if you are intrested in helping me.

- also see Download section

Resource usage


Rx Channel Block: which includes HDLC Framing extraction, zero removal and conversion from serial to parallel.

Vendor Device Size Frequency  Board Tested Functional Test Notes
Altera EP20K100BC356-3 108 LCs 91.48MHz - - No optimization was peroformed, using Quartus II

Tx Channel Block: which includes HDLC Frame generation, zero insertion and conversion from parallel to serial.
Vendor Device Size Frequency  Board Tested Functional Test Notes
Altera EP20K100BC356-3 100 LCs 112.42MHz - - No optimization was peroformed, using Quartus II

HDLC controller Block: which includes both the Rx and Tx channels, FCS-16 generation and checking, 128 byte buffering for each direction and Wishbon SOC bus interface and controller registers.
Vendor Device Size Frequencies (MHz) Board Tested Functional Test Notes
Altera EP20K100BC356-3 630 LCs, 2 ESBs CLK_I=74.02, RxClk=101.86, TxClk=106.42 - - No optimization was peroformed, using Quartus II

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