OpenCores

HIVE - a 32 bit, 8 thread, 4 register/stack hybrid, pipelined verilog soft processor core

News
Sep 7, 2015Project page updated to reflect v08.06 codeWallin, Eric
Oct 10, 2014Added quick link to Excel-based HIVE processor simulatorWallin, Eric
Sep 16, 2014Hive v06.01 SV and design document updatedWallin, Eric
Jun 17, 2014v05.04 is now written in synthesizable SystemVerilog!Wallin, Eric
Jun 8, 2014sim linkWallin, Eric
Jun 8, 2014v05.03 newsWallin, Eric
Jan 8, 2014Updated description textWallin, Eric
Jan 6, 2014Update to reflect v04.05Wallin, Eric
Jul 7, 2013Added latest code version and design document.Wallin, Eric
Jun 25, 2013All opcodes have been checked for correct functioning.Wallin, Eric
Jun 23, 2013Added design documentWallin, Eric
Jun 23, 2013Added descriptionWallin, Eric