OpenCores

*I2C controller core :: Bugtracker

Request(s)
Date Title Status Assigned to Submitted by
Jul 2, 2015 Clock prescaler OPENED jgiampiccolo
Nov 4, 2014 Please consider updating prescaler documentation OPENED TAEvans
Jul 29, 2014 SMBus compliant? OPENED shankar517
Mar 19, 2014 Arbitration lost for slow I2C slaves OPENED viktor_bergen
Apr 18, 2013 ACK not sent for all read bytes OPENED rherveille xweing
Feb 16, 2013 No Acknowledgment CLOSED mokhoo
Aug 8, 2012 unused register bit removal OPENED adyer
Jul 11, 2012 about zhe code CLOSED ivay
Nov 9, 2011 how to initialize i2c_busy OPENED wojtAS
Oct 24, 2011 OPENED vickyxia
Sep 30, 2010 Documentation of VHDL for output buffers CLOSED Schwirz
Aug 30, 2010 Arbitration lost OPENED cheevu
Jul 1, 2010 sequence to read RxAck from status register OPENED allamovich_1
Jul 1, 2010 how to read from status register CLOSED allamovich_1
May 4, 2010 Slave mode OPENED janoukie
Sep 3, 2009 Arbitration problem CLOSED rherveille pignoffo
Jul 10, 2009 The core DO NOT support large i2c slave? CLOSED markman
Jun 6, 2009 I2C core and Max Wishbone frequency CLOSED gerry
Bug(s)
Date Title Status Assigned to Submitted by
Jul 20, 2015 Wrong fast_tsu_sta OPENED ysdn
Jun 2, 2015 I2C slave model - sda_o fixed output OPENED Evripidis
Nov 13, 2014 I2C Clock/Data Rate Runs Slow due to Stretch Code OPENED TAEvans
Nov 4, 2014 Arb Lost due to Clock Stretch detection failure OPENED TAEvans
Apr 9, 2013 TIP bit not set when generating STOP condition CLOSED shuckc
Feb 16, 2013 Prescaler CLOSED mokhoo
Jun 8, 2011 i2c_slave_model is not a synthesizable code CLOSED jerry_hsu
Jun 8, 2011 i2c_slave_model invalid slave address will issue a error write OPENED jerry_hsu
Dec 4, 2010 bit_controller state machine o/ps CLOSED pranavverma
Aug 6, 2010 Presacler or Documentation wrong OPENED but5693
May 31, 2010 Init filter_cnt CLOSED rherveille jon_vdb
Mar 5, 2010 wrong copy/paste CLOSED rherveille cbeguet
Mar 4, 2010 Missing Library CLOSED cbeguet
Jul 3, 2009 blocking and non-blocking CLOSED rherveille markman
Jun 1, 2009 WISHBONE Bus captures write data twice. CLOSED rherveille rehayes
Apr 30, 2009 extra SCL tick CLOSED rherveille stustuff123
Feb 12, 2009 Arbitration error in (vhdl) version 1.17 of the i2c_master_bit_ctrl CLOSED rherveille awijsmuller
Jan 29, 2009 project lists under VHDL ...but no VHDL DELETED rherveille poppafuze
Jan 20, 2009 scl_oen? DELETED rherveille olaf.vandenberg
Nov 3, 2008 Strange I2C behavior (reads->writes) CLOSED rherveille galland
Aug 9, 2008 Repeated Start Tsu OPENED rherveille vackovik@yahoo.com
Jul 26, 2008 Clock synchronization for multi-master system CLOSED rherveille ivanlawrow@yahoo.com
Apr 9, 2008 Lacking example and erroneous example? CLOSED wzab@ise.pw.edu.pl
May 25, 2007 START doesn't satisfy Timing Requirements? CLOSED rherveille jeremy.hannon@ge.com
Aug 4, 2004 testbench error CLOSED rherveille kelvin_bao@163.com
Feb 10, 2004 Testbench error CLOSED rherveille martin.j.thompson@trw.com
Idea(s)
Date Title Status Assigned to Submitted by
Feb 10, 2004 NUMERIC_STD CLOSED martin.j.thompson@trw.com
Reminder(s)
Date Title Status Assigned to Submitted by
Jun 17, 2016 oc_i2c_master.h: wrong ACK-bit definition OPENED wyzzz
Mar 30, 2011 copy/paste error? CLOSED jerry_hsu
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