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Implementation of Cube Root of a fixed point number on FPGA :: Overview

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Details

Name: implementation_of_cube_root_of_a_fixed_point_number_on_fpga
Created: Jul 5, 2015
Updated: Jul 2, 2017
SVN: No files checked in

Other project properties

Category: Arithmetic core
Language: Verilog
Development status: Stable
Additional info: none
WishBone compliant: No
WishBone version: n/a
License: LGPL

Description

Hardware implementation of cube root algorithm with shift-and-add operations for optimisation. Achieved higher clock speed, throughput and turnaround time than previous implementations by using pipelined architecture.

Code

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:26:53 10/26/2013
// Design Name:
// Module Name: CubeRoot
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module CubeRoot(Number, clk, Answer, Remainder, NumberLevel1, NumberLevel2, NumberLevel3, NumberLevel4, NumberLevel5, NumberLevel6, NumberLevel7, NumberLevel8, NumberLevel9, NumberLevel10);

input [63:0] Number;
input clk;
output [21:0] Answer;
output [63:0] Remainder;
output NumberLevel1, NumberLevel2, NumberLevel3, NumberLevel4, NumberLevel5, NumberLevel6, NumberLevel7, NumberLevel8, NumberLevel9, NumberLevel10;

// First Level //////////////////////////////////////////////////////////////////////////////////////////////////////////

reg [3:0] Add1Level1;
wire [3:0] Add1Level1Wire = Add1Level1;

always @* begin
Add1Level1 = {2'b0, Number[63]} - 3'd1;
end

reg [63:0] NumberLevel1;
reg AnswerLevel1;

always @(posedge clk) begin
if(!Add1Level1Wire[3]) begin
NumberLevel1 end
else begin
NumberLevel1 end
AnswerLevel1 end

reg [4:0] Add2Level1;
wire [4:0] Add2Level1Wire = Add2Level1;

always @* begin
Add2Level1 = {!Add1Level1Wire[3], 4'b0} + {!Add1Level1Wire, 1'b0};
end

reg [2:0] Add3Level1;
wire [2:0] Add3Level1Wire = Add3Level1;

always @* begin
Add3Level1 = {!Add1Level1Wire[3], 2'b0} + {!Add1Level1Wire, 1'b0};
end

reg [4:0] Add4Level1;
wire [4:0] Add4Level1Wire = Add4Level1;

always @* begin
if(!Add1Level1Wire[3]) begin
Add4Level1 = 1 + Add2Level1Wire;
end
else begin
Add4Level1 = 1 - Add3Level1Wire;
end
end

reg [4:0] PLevel1;

always @(posedge clk) begin
PLevel1 end

// Second Level /////////////////////////////////////////////////////////////////////////////////////////////////////////

reg [6:0] Add1Level2;
wire [6:0] Add1Level2Wire = Add1Level2;

always @* begin
Add1Level2 = {2'b0, NumberLevel1[63:60]} - PLevel1;
end

reg [63:0] NumberLevel2;
reg [1:0] AnswerLevel2;

always @(posedge clk) begin
if(!Add1Level2Wire[6]) begin
NumberLevel2 end
else begin
NumberLevel2 end
AnswerLevel2 end

reg [5:0] Add2Level2;
wire [5:0] Add2Level2Wire = Add2Level2;

always @* begin
Add2Level2 = {AnswerLevel1, !Add1Level2Wire[6], 4'b0} + {AnswerLevel1, !Add1Level2Wire[6], 1'b0};
end

reg [6:0] Add3Level2;
wire [6:0] Add3Level2Wire = Add3Level2;

always @* begin
Add3Level2 = {AnswerLevel1, !Add1Level2Wire[6], 2'b0} + {AnswerLevel1, !Add1Level2Wire[6], 1'b0};
end

reg [4:0] Add4Level2;
wire [4:0] Add4Level2Wire = Add4Level2;

always @* begin
Add4Level2 = {PLevel1, 2'b0} - 3;
end

reg [6:0] Add5Level2;
wire [6:0] Add5Level2Wire = Add5Level2;

always @* begin
if(!Add1Level2Wire[6]) begin
Add5Level2 = Add4Level2Wire + Add2Level2Wire;
end
else begin
Add5Level2 = Add4Level2Wire - Add3Level2Wire;
end
end

reg [6:0] PLevel2;

always @(posedge clk) begin
PLevel2 end

// Third Level /////////////////////////////////////////////////////////////////////////////////////////////////////////

reg [9:0] Add1Level3;
wire [9:0] Add1Level3Wire = Add1Level3;

always @* begin
Add1Level3 = {2'b0, NumberLevel2[63:57]} - PLevel2;
end

reg [63:0] NumberLevel3;
reg [2:0] AnswerLevel3;

always @(posedge clk) begin
if(!Add1Level3Wire[9]) begin
NumberLevel3 end
else begin
NumberLevel3 end
AnswerLevel3 end

reg [6:0] Add2Level3;
wire [6:0] Add2Level3Wire = Add2Level3;

always @* begin
Add2Level3 = {AnswerLevel2, !Add1Level3Wire[9], 4'b0} + {AnswerLevel2, !Add1Level3Wire[9], 1'b0};
end

reg [5:0] Add3Level3;
wire [5:0] Add3Level3Wire = Add3Level3;

always @* begin
Add3Level3 = {AnswerLevel2, !Add1Level3Wire[9], 2'b0} + {AnswerLevel2, !Add1Level3Wire[9], 1'b0};
end

reg [8:0] Add4Level3;
wire [8:0] Add4Level3Wire = Add4Level3;

always @* begin
Add4Level3 = {PLevel2, 2'b0} - 3;
end

reg [9:0] Add5Level3;
wire [9:0] Add5Level3Wire = Add5Level3;

always @* begin
if(!Add1Level3Wire[9]) begin
Add5Level3 = Add4Level3Wire + Add2Level3Wire;
end
else begin
Add5Level3 = Add4Level3Wire - Add3Level3Wire;
end
end

reg [9:0] PLevel3;

always @(posedge clk) begin
PLevel3 end

// Fourth Level /////////////////////////////////////////////////////////////////////////////////////////////////////////

reg [12:0] Add1Level4;
wire [12:0] Add1Level4Wire = Add1Level4;

always @* begin
Add1Level4 = {2'b0, NumberLevel3[63:54]} - PLevel3;
end

reg [63:0] NumberLevel4;
reg [3:0] AnswerLevel4;

always @(posedge clk) begin
if(!Add1Level4Wire[12]) begin
NumberLevel4 end
else begin
NumberLevel4 end
AnswerLevel4 end

reg [8:0] Add2Level4;
wire [8:0] Add2Level4Wire = Add2Level4;

always @* begin
Add2Level4 = {AnswerLevel3, !Add1Level4Wire[12], 4'b0} + {AnswerLevel3, !Add1Level4Wire[12], 1'b0};
end

reg [6:0] Add3Level4;
wire [6:0] Add3Level4Wire = Add3Level4;

always @* begin
Add3Level4 = {AnswerLevel3, !Add1Level4Wire[12], 2'b0} + {AnswerLevel3, !Add1Level4Wire[12], 1'b0};
end

reg [11:0] Add4Level4;
wire [11:0] Add4Level4Wire = Add4Level4;

always @* begin
Add4Level4 = {PLevel3, 2'b0} - 3;
end

reg [11:0] Add5Level4;
wire [11:0] Add5Level4Wire = Add5Level4;

always @* begin
if(!Add1Level4Wire[12]) begin
Add5Level4 = Add4Level4Wire + Add2Level4Wire;
end
else begin
Add5Level4 = Add4Level4Wire - Add3Level4Wire;
end
end

reg [11:0] PLevel4;

always @(posedge clk) begin
PLevel4 end

// Fifth Level /////////////////////////////////////////////////////////////////////////////////////////////////////////

reg [15:0] Add1Level5;
wire [15:0] Add1Level5Wire = Add1Level5;

always @* begin
Add1Level5 = {2'b0, NumberLevel4[63:51]} - PLevel4;
end

reg [63:0] NumberLevel5;
reg [4:0] AnswerLevel5;

always @(posedge clk) begin
if(!Add1Level5Wire[15]) begin
NumberLevel5 end
else begin
NumberLevel5 end
AnswerLevel5 end

reg [9:0] Add2Level5;
wire [9:0] Add2Level5Wire = Add2Level5;

always @* begin
Add2Level5 = {AnswerLevel4, !Add1Level5Wire[15], 4'b0} + {AnswerLevel4, !Add1Level5Wire[15], 1'b0};
end

reg [7:0] Add3Level5;
wire [7:0] Add3Level5Wire = Add3Level5;

always @* begin
Add3Level5 = {AnswerLevel4, !Add1Level5Wire[15], 2'b0} + {AnswerLevel4, !Add1Level5Wire[15], 1'b0};
end

reg [13:0] Add4Level5;
wire [13:0] Add4Level5Wire = Add4Level5;

always @* begin
Add4Level5 = {PLevel4, 2'b0} - 3;
end

reg [13:0] Add5Level5;
wire [13:0] Add5Level5Wire = Add5Level5;

always @* begin
if(!Add1Level5Wire[12]) begin
Add5Level5 = Add4Level5Wire + Add2Level5Wire;
end
else begin
Add5Level5 = Add4Level5Wire - Add3Level5Wire;
end
end

reg [13:0] PLevel5;

always @(posedge clk) begin
PLevel5 end

// Sixth Level /////////////////////////////////////////////////////////////////////////////////////////////////////////

reg [18:0] Add1Level6;
wire [18:0] Add1Level6Wire = Add1Level6;

always @* begin
Add1Level6 = {2'b0, NumberLevel5[63:48]} - PLevel5;
end

reg [63:0] NumberLevel6;
reg [5:0] AnswerLevel6;

always @(posedge clk) begin
if(!Add1Level6Wire[18]) begin
NumberLevel6 end
else begin
NumberLevel6 end
AnswerLevel6 end

reg [10:0] Add2Level6;
wire [10:0] Add2Level6Wire = Add2Level6;

always @* begin
Add2Level6 = {AnswerLevel5, !Add1Level6Wire[18], 4'b0} + {AnswerLevel5, !Add1Level6Wire[18], 1'b0};
end

reg [8:0] Add3Level6;
wire [8:0] Add3Level6Wire = Add3Level6;

always @* begin
Add3Level6 = {AnswerLevel5, !Add1Level6Wire[18], 2'b0} + {AnswerLevel5, !Add1Level6Wire[18], 1'b0};
end

reg [15:0] Add4Level6;
wire [15:0] Add4Level6Wire = Add4Level6;

always @* begin
Add4Level6 = {PLevel5, 2'b0} - 3;
end

reg [15:0] Add5Level6;
wire [15:0] Add5Level6Wire = Add5Level6;

always @* begin
if(!Add1Level6Wire[18]) begin
Add5Level6 = Add4Level6Wire + Add2Level6Wire;
end
else begin
Add5Level6 = Add4Level6Wire - Add3Level6Wire;
end
end

reg [15:0] PLevel6;

always @(posedge clk) begin
PLevel6 end

// Seventh Level /////////////////////////////////////////////////////////////////////////////////////////////////////////

reg [21:0] Add1Level7;
wire [21:0] Add1Level7Wire = Add1Level7;

always @* begin
Add1Level7 = {2'b0, NumberLevel6[63:45]} - PLevel6;
end

reg [63:0] NumberLevel7;
reg [6:0] AnswerLevel7;

always @(posedge clk) begin
if(!Add1Level7Wire[21]) begin
NumberLevel7 end
else begin
NumberLevel7 end
AnswerLevel7 end

reg [11:0] Add2Level7;
wire [11:0] Add2Level7Wire = Add2Level7;

always @* begin
Add2Level7 = {AnswerLevel6, !Add1Level7Wire[21], 4'b0} + {AnswerLevel6, !Add1Level7Wire[21], 1'b0};
end

reg [9:0] Add3Level7;
wire [9:0] Add3Level7Wire = Add3Level7;

always @* begin
Add3Level7 = {AnswerLevel6, !Add1Level7Wire[21], 2'b0} + {AnswerLevel6, !Add1Level7Wire[21], 1'b0};
end

reg [17:0] Add4Level7;
wire [17:0] Add4Level7Wire = Add4Level7;

always @* begin
Add4Level7 = {PLevel6, 2'b0} - 3;
end

reg [17:0] Add5Level7;
wire [17:0] Add5Level7Wire = Add5Level7;

always @* begin
if(!Add1Level7Wire[21]) begin
Add5Level7 = Add4Level7Wire + Add2Level7Wire;
end
else begin
Add5Level7 = Add4Level7Wire - Add3Level7Wire;
end
end

reg [17:0] PLevel7;

always @(posedge clk) begin
PLevel7 end

// Eighth Level /////////////////////////////////////////////////////////////////////////////////////////////////////////

reg [24:0] Add1Level8;
wire [24:0] Add1Level8Wire = Add1Level8;

always @* begin
Add1Level8 = {2'b0, NumberLevel7[63:42]} - PLevel7;
end

reg [63:0] NumberLevel8;
reg [7:0] AnswerLevel8;

always @(posedge clk) begin
if(!Add1Level8Wire[24]) begin
NumberLevel8 end
else begin
NumberLevel8 end
AnswerLevel8 end

reg [12:0] Add2Level8;
wire [12:0] Add2Level8Wire = Add2Level8;

always @* begin
Add2Level8 = {AnswerLevel7, !Add1Level8Wire[24], 4'b0} + {AnswerLevel7, !Add1Level8Wire[24], 1'b0};
end

reg [10:0] Add3Level8;
wire [10:0] Add3Level8Wire = Add3Level8;

always @* begin
Add3Level8 = {AnswerLevel7, !Add1Level8Wire[24], 2'b0} + {AnswerLevel7, !Add1Level8Wire[24], 1'b0};
end

reg [19:0] Add4Level8;
wire [19:0] Add4Level8Wire = Add4Level8;

always @* begin
Add4Level8 = {PLevel7, 2'b0} - 3;
end

reg [19:0] Add5Level8;
wire [19:0] Add5Level8Wire = Add5Level8;

always @* begin
if(!Add1Level8Wire[24]) begin
Add5Level8 = Add4Level8Wire + Add2Level8Wire;
end
else begin
Add5Level8 = Add4Level8Wire - Add3Level8Wire;
end
end

reg [19:0] PLevel8;

always @(posedge clk) begin
PLevel8 end

// Ninth Level /////////////////////////////////////////////////////////////////////////////////////////////////////////

reg [27:0] Add1Level9;
wire [27:0] Add1Level9Wire = Add1Level9;

always @* begin
Add1Level9 = {2'b0, NumberLevel8[63:39]} - PLevel8;
end

reg [63:0] NumberLevel9;
reg [8:0] AnswerLevel9;

always @(posedge clk) begin
if(!Add1Level9Wire[27]) begin
NumberLevel9 end
else begin
NumberLevel9 end
AnswerLevel9 end

reg [13:0] Add2Level9;
wire [13:0] Add2Level9Wire = Add2Level9;

always @* begin
Add2Level9 = {AnswerLevel8, !Add1Level9Wire[27], 4'b0} + {AnswerLevel8, !Add1Level9Wire[27], 1'b0};
end

reg [11:0] Add3Level9;
wire [11:0] Add3Level9Wire = Add3Level9;

always @* begin
Add3Level9 = {AnswerLevel8, !Add1Level9Wire[27], 2'b0} + {AnswerLevel8, !Add1Level9Wire[27], 1'b0};
end

reg [21:0] Add4Level9;
wire [21:0] Add4Level9Wire = Add4Level9;

always @* begin
Add4Level9 = {PLevel8, 2'b0} - 3;
end

reg [21:0] Add5Level9;
wire [21:0] Add5Level9Wire = Add5Level9;

always @* begin
if(!Add1Level9Wire[27]) begin
Add5Level9 = Add4Level9Wire + Add2Level9Wire;
end
else begin
Add5Level9 = Add4Level9Wire - Add3Level9Wire;
end
end

reg [21:0] PLevel9;

always @(posedge clk) begin
PLevel9 end

// Tenth Level /////////////////////////////////////////////////////////////////////////////////////////////////////////

reg [30:0] Add1Level10;
wire [30:0] Add1Level10Wire = Add1Level10;

always @* begin
Add1Level10 = {2'b0, NumberLevel9[63:36]} - PLevel9;
end

reg [63:0] NumberLevel10;
reg [9:0] AnswerLevel10;

always @(posedge clk) begin
if(!Add1Level10Wire[30]) begin
NumberLevel10 end
else begin
NumberLevel10 end
AnswerLevel10 end

reg [14:0] Add2Level10;
wire [14:0] Add2Level10Wire = Add2Level10;

always @* begin
Add2Level10 = {AnswerLevel9, !Add1Level10Wire[30], 4'b0} + {AnswerLevel9, !Add1Level10Wire[30], 1'b0};
end

reg [12:0] Add3Level10;
wire [12:0] Add3Level10Wire = Add3Level10;

always @* begin
Add3Level10 = {AnswerLevel9, !Add1Level10Wire[30], 2'b0} + {AnswerLevel9, !Add1Level10Wire[30], 1'b0};
end

reg [23:0] Add4Level10;
wire [23:0] Add4Level10Wire = Add4Level10;

always @* begin
Add4Level10 = {PLevel9, 2'b0} - 3;
end

reg [23:0] Add5Level10;
wire [23:0] Add5Level10Wire = Add5Level10;

always @* begin
if(!Add1Level10Wire[30]) begin
Add5Level10 = Add4Level10Wire + Add2Level10Wire;
end
else begin
Add5Level10 = Add4Level10Wire - Add3Level10Wire;
end
end

reg [23:0] PLevel10;

always @(posedge clk) begin
PLevel10 end

// Eleventh Level /////////////////////////////////////////////////////////////////////////////////////////////////////////

reg [33:0] Add1Level11;
wire [33:0] Add1Level11Wire = Add1Level11;

always @* begin
Add1Level11 = {2'b0, NumberLevel10[63:33]} - PLevel10;
end

reg [63:0] NumberLevel11;
reg [10:0] AnswerLevel11;

always @(posedge clk) begin
if(!Add1Level11Wire[33]) begin
NumberLevel11 end
else begin
NumberLevel11 end
AnswerLevel11 end

reg [15:0] Add2Level11;
wire [15:0] Add2Level11Wire = Add2Level11;

always @* begin
Add2Level11 = {AnswerLevel10, !Add1Level11Wire[33], 4'b0} + {AnswerLevel10, !Add1Level11Wire[33], 1'b0};
end

reg [13:0] Add3Level11;
wire [13:0] Add3Level11Wire = Add3Level11;

always @* begin
Add3Level11 = {AnswerLevel10, !Add1Level11Wire[33], 2'b0} + {AnswerLevel10, !Add1Level11Wire[33], 1'b0};
end

reg [25:0] Add4Level11;
wire [25:0] Add4Level11Wire = Add4Level11;

always @* begin
Add4Level11 = {PLevel10, 2'b0} - 3;
end

reg [25:0] Add5Level11;
wire [25:0] Add5Level11Wire = Add5Level11;

always @* begin
if(!Add1Level11Wire[33]) begin
Add5Level11 = Add4Level11Wire + Add2Level11Wire;
end
else begin
Add5Level11 = Add4Level11Wire - Add3Level11Wire;
end
end

reg [25:0] PLevel11;

always @(posedge clk) begin
PLevel11 end

// Twelveth Level /////////////////////////////////////////////////////////////////////////////////////////////////////////

reg [36:0] Add1Level12;
wire [36:0] Add1Level12Wire = Add1Level12;

always @* begin
Add1Level12 = {2'b0, NumberLevel11[63:30]} - PLevel11;
end

reg [63:0] NumberLevel12;
reg [11:0] AnswerLevel12;

always @(posedge clk) begin
if(!Add1Level12Wire[36]) begin
NumberLevel12 end
else begin
NumberLevel12 end
AnswerLevel12 end

reg [16:0] Add2Level12;
wire [16:0] Add2Level12Wire = Add2Level12;

always @* begin
Add2Level12 = {AnswerLevel11, !Add1Level12Wire[36], 4'b0} + {AnswerLevel11, !Add1Level12Wire[36], 1'b0};
end

reg [14:0] Add3Level12;
wire [14:0] Add3Level12Wire = Add3Level12;

always @* begin
Add3Level12 = {AnswerLevel11, !Add1Level12Wire[36], 2'b0} + {AnswerLevel11, !Add1Level12Wire[36], 1'b0};
end

reg [27:0] Add4Level12;
wire [27:0] Add4Level12Wire = Add4Level12;

always @* begin
Add4Level12 = {PLevel11, 2'b0} - 3;
end

reg [27:0] Add5Level12;
wire [27:0] Add5Level12Wire = Add5Level12;

always @* begin
if(!Add1Level12Wire[36]) begin
Add5Level12 = Add4Level12Wire + Add2Level12Wire;
end
else begin
Add5Level12 = Add4Level12Wire - Add3Level12Wire;
end
end

reg [27:0] PLevel12;

always @(posedge clk) begin
PLevel12 end

// Thirteenth Level /////////////////////////////////////////////////////////////////////////////////////////////////////////

reg [39:0] Add1Level13;
wire [39:0] Add1Level13Wire = Add1Level13;

always @* begin
Add1Level13 = {2'b0, NumberLevel12[63:27]} - PLevel12;
end

reg [63:0] NumberLevel13;
reg [12:0] AnswerLevel13;

always @(posedge clk) begin
if(!Add1Level13Wire[39]) begin
NumberLevel13 end
else begin
NumberLevel13 end
AnswerLevel13 end

reg [17:0] Add2Level13;
wire [17:0] Add2Level13Wire = Add2Level13;

always @* begin
Add2Level13 = {AnswerLevel12, !Add1Level13Wire[39], 4'b0} + {AnswerLevel12, !Add1Level13Wire[39], 1'b0};
end

reg [15:0] Add3Level13;
wire [15:0] Add3Level13Wire = Add3Level13;

always @* begin
Add3Level13 = {AnswerLevel12, !Add1Level13Wire[39], 2'b0} + {AnswerLevel12, !Add1Level13Wire[39], 1'b0};
end

reg [29:0] Add4Level13;
wire [29:0] Add4Level13Wire = Add4Level13;

always @* begin
Add4Level13 = {PLevel12, 2'b0} - 3;
end

reg [29:0] Add5Level13;
wire [29:0] Add5Level13Wire = Add5Level13;

always @* begin
if(!Add1Level13Wire[39]) begin
Add5Level13 = Add4Level13Wire + Add2Level13Wire;
end
else begin
Add5Level13 = Add4Level13Wire - Add3Level13Wire;
end
end

reg [29:0] PLevel13;

always @(posedge clk) begin
PLevel13 end

// Fourteenth Level /////////////////////////////////////////////////////////////////////////////////////////////////////////

reg [42:0] Add1Level14;
wire [42:0] Add1Level14Wire = Add1Level14;

always @* begin
Add1Level14 = {2'b0, NumberLevel13[63:24]} - PLevel13;
end

reg [63:0] NumberLevel14;
reg [13:0] AnswerLevel14;

always @(posedge clk) begin
if(!Add1Level14Wire[42]) begin
NumberLevel14 end
else begin
NumberLevel14 end
AnswerLevel14 end

reg [18:0] Add2Level14;
wire [18:0] Add2Level14Wire = Add2Level14;

always @* begin
Add2Level14 = {AnswerLevel13, !Add1Level14Wire[42], 4'b0} + {AnswerLevel13, !Add1Level14Wire[42], 1'b0};
end

reg [16:0] Add3Level14;
wire [16:0] Add3Level14Wire = Add3Level14;

always @* begin
Add3Level14 = {AnswerLevel13, !Add1Level14Wire[42], 2'b0} + {AnswerLevel13, !Add1Level14Wire[42], 1'b0};
end

reg [31:0] Add4Level14;
wire [31:0] Add4Level14Wire = Add4Level14;

always @* begin
Add4Level14 = {PLevel13, 2'b0} - 3;
end

reg [31:0] Add5Level14;
wire [31:0] Add5Level14Wire = Add5Level14;

always @* begin
if(!Add1Level14Wire[42]) begin
Add5Level14 = Add4Level14Wire + Add2Level14Wire;
end
else begin
Add5Level14 = Add4Level14Wire - Add3Level14Wire;
end
end

reg [31:0] PLevel14;

always @(posedge clk) begin
PLevel14 end


// Fifteenth Level /////////////////////////////////////////////////////////////////////////////////////////////////////////

reg [45:0] Add1Level15;
wire [45:0] Add1Level15Wire = Add1Level15;

always @* begin
Add1Level15 = {2'b0, NumberLevel14[63:21]} - PLevel14;
end

reg [63:0] NumberLevel15;
reg [14:0] AnswerLevel15;

always @(posedge clk) begin
if(!Add1Level15Wire[45]) begin
NumberLevel15 end
else begin
NumberLevel15 end
AnswerLevel15 end

reg [19:0] Add2Level15;
wire [19:0] Add2Level15Wire = Add2Level15;

always @* begin
Add2Level15 = {AnswerLevel14, !Add1Level15Wire[45], 4'b0} + {AnswerLevel14, !Add1Level15Wire[45], 1'b0};
end

reg [17:0] Add3Level15;
wire [17:0] Add3Level15Wire = Add3Level15;

always @* begin
Add3Level15 = {AnswerLevel14, !Add1Level15Wire[45], 2'b0} + {AnswerLevel14, !Add1Level15Wire[45], 1'b0};
end

reg [33:0] Add4Level15;
wire [33:0] Add4Level15Wire = Add4Level15;

always @* begin
Add4Level15 = {PLevel14, 2'b0} - 3;
end

reg [33:0] Add5Level15;
wire [33:0] Add5Level15Wire = Add5Level15;

always @* begin
if(!Add1Level15Wire[45]) begin
Add5Level15 = Add4Level15Wire + Add2Level15Wire;
end
else begin
Add5Level15 = Add4Level15Wire - Add3Level15Wire;
end
end

reg [33:0] PLevel15;

always @(posedge clk) begin
PLevel15 end

// Sixteenth Level /////////////////////////////////////////////////////////////////////////////////////////////////////////

reg [48:0] Add1Level16;
wire [48:0] Add1Level16Wire = Add1Level16;

always @* begin
Add1Level16 = {2'b0, NumberLevel15[63:18]} - PLevel15;
end

reg [63:0] NumberLevel16;
reg [15:0] AnswerLevel16;

always @(posedge clk) begin
if(!Add1Level16Wire[48]) begin
NumberLevel16 end
else begin
NumberLevel16 end
AnswerLevel16 end

reg [20:0] Add2Level16;
wire [20:0] Add2Level16Wire = Add2Level16;

always @* begin
Add2Level16 = {AnswerLevel15, !Add1Level16Wire[48], 4'b0} + {AnswerLevel15, !Add1Level16Wire[48], 1'b0};
end

reg [18:0] Add3Level16;
wire [18:0] Add3Level16Wire = Add3Level16;

always @* begin
Add3Level16 = {AnswerLevel15, !Add1Level16Wire[48], 2'b0} + {AnswerLevel15, !Add1Level16Wire[48], 1'b0};
end

reg [35:0] Add4Level16;
wire [35:0] Add4Level16Wire = Add4Level16;

always @* begin
Add4Level16 = {PLevel15, 2'b0} - 3;
end

reg [35:0] Add5Level16;
wire [35:0] Add5Level16Wire = Add5Level16;

always @* begin
if(!Add1Level16Wire[48]) begin
Add5Level16 = Add4Level16Wire + Add2Level16Wire;
end
else begin
Add5Level16 = Add4Level16Wire - Add3Level16Wire;
end
end

reg [35:0] PLevel16;

always @(posedge clk) begin
PLevel16 end

// Seventeenth Level /////////////////////////////////////////////////////////////////////////////////////////////////////////

reg [51:0] Add1Level17;
wire [51:0] Add1Level17Wire = Add1Level17;

always @* begin
Add1Level17 = {2'b0, NumberLevel16[63:15]} - PLevel16;
end

reg [63:0] NumberLevel17;
reg [16:0] AnswerLevel17;

always @(posedge clk) begin
if(!Add1Level17Wire[51]) begin
NumberLevel17 end
else begin
NumberLevel17 end
AnswerLevel17 end

reg [21:0] Add2Level17;
wire [21:0] Add2Level17Wire = Add2Level17;

always @* begin
Add2Level17 = {AnswerLevel16, !Add1Level17Wire[51], 4'b0} + {AnswerLevel16, !Add1Level17Wire[51], 1'b0};
end

reg [19:0] Add3Level17;
wire [19:0] Add3Level17Wire = Add3Level17;

always @* begin
Add3Level17 = {AnswerLevel16, !Add1Level17Wire[51], 2'b0} + {AnswerLevel16, !Add1Level17Wire[51], 1'b0};
end

reg [37:0] Add4Level17;
wire [37:0] Add4Level17Wire = Add4Level17;

always @* begin
Add4Level17 = {PLevel16, 2'b0} - 3;
end

reg [37:0] Add5Level17;
wire [37:0] Add5Level17Wire = Add5Level17;

always @* begin
if(!Add1Level17Wire[51]) begin
Add5Level17 = Add4Level17Wire + Add2Level17Wire;
end
else begin
Add5Level17 = Add4Level17Wire - Add3Level17Wire;
end
end

reg [37:0] PLevel17;

always @(posedge clk) begin
PLevel17 end

// Eighteenth Level /////////////////////////////////////////////////////////////////////////////////////////////////////////

reg [54:0] Add1Level18;
wire [54:0] Add1Level18Wire = Add1Level18;

always @* begin
Add1Level18 = {2'b0, NumberLevel17[63:12]} - PLevel17;
end

reg [63:0] NumberLevel18;
reg [17:0] AnswerLevel18;

always @(posedge clk) begin
if(!Add1Level18Wire[54]) begin
NumberLevel18 end
else begin
NumberLevel18 end
AnswerLevel18 end

reg [22:0] Add2Level18;
wire [22:0] Add2Level18Wire = Add2Level18;

always @* begin
Add2Level18 = {AnswerLevel17, !Add1Level18Wire[54], 4'b0} + {AnswerLevel17, !Add1Level18Wire[54], 1'b0};
end

reg [20:0] Add3Level18;
wire [20:0] Add3Level18Wire = Add3Level18;

always @* begin
Add3Level18 = {AnswerLevel17, !Add1Level18Wire[54], 2'b0} + {AnswerLevel17, !Add1Level18Wire[54], 1'b0};
end

reg [39:0] Add4Level18;
wire [39:0] Add4Level18Wire = Add4Level18;

always @* begin
Add4Level18 = {PLevel17, 2'b0} - 3;
end

reg [39:0] Add5Level18;
wire [39:0] Add5Level18Wire = Add5Level18;

always @* begin
if(!Add1Level18Wire[54]) begin
Add5Level18 = Add4Level18Wire + Add2Level18Wire;
end
else begin
Add5Level18 = Add4Level18Wire - Add3Level18Wire;
end
end

reg [39:0] PLevel18;

always @(posedge clk) begin
PLevel18 end


// Nineteenth Level /////////////////////////////////////////////////////////////////////////////////////////////////////////

reg [57:0] Add1Level19;
wire [57:0] Add1Level19Wire = Add1Level19;

always @* begin
Add1Level19 = {2'b0, NumberLevel18[63:9]} - PLevel18;
end

reg [63:0] NumberLevel19;
reg [18:0] AnswerLevel19;

always @(posedge clk) begin
if(!Add1Level19Wire[57]) begin
NumberLevel19 end
else begin
NumberLevel19 end
AnswerLevel19 end

reg [23:0] Add2Level19;
wire [23:0] Add2Level19Wire = Add2Level19;

always @* begin
Add2Level19 = {AnswerLevel18, !Add1Level19Wire[57], 4'b0} + {AnswerLevel18, !Add1Level19Wire[57], 1'b0};
end

reg [21:0] Add3Level19;
wire [21:0] Add3Level19Wire = Add3Level19;

always @* begin
Add3Level19 = {AnswerLevel18, !Add1Level19Wire[57], 2'b0} + {AnswerLevel18, !Add1Level19Wire[57], 1'b0};
end

reg [41:0] Add4Level19;
wire [41:0] Add4Level19Wire = Add4Level19;

always @* begin
Add4Level19 = {PLevel18, 2'b0} - 3;
end

reg [41:0] Add5Level19;
wire [41:0] Add5Level19Wire = Add5Level19;

always @* begin
if(!Add1Level19Wire[57]) begin
Add5Level19 = Add4Level19Wire + Add2Level19Wire;
end
else begin
Add5Level19 = Add4Level19Wire - Add3Level19Wire;
end
end

reg [41:0] PLevel19;

always @(posedge clk) begin
PLevel19 end

// Twentyth Level /////////////////////////////////////////////////////////////////////////////////////////////////////////

reg [60:0] Add1Level20;
wire [60:0] Add1Level20Wire = Add1Level20;

always @* begin
Add1Level20 = {2'b0, NumberLevel19[63:6]} - PLevel19;
end

reg [63:0] NumberLevel20;
reg [19:0] AnswerLevel20;

always @(posedge clk) begin
if(!Add1Level20Wire[60]) begin
NumberLevel20 end
else begin
NumberLevel20 end
AnswerLevel20 end

reg [24:0] Add2Level20;
wire [24:0] Add2Level20Wire = Add2Level20;

always @* begin
Add2Level20 = {AnswerLevel19, !Add1Level20Wire[60], 4'b0} + {AnswerLevel19, !Add1Level20Wire[60], 1'b0};
end

reg [22:0] Add3Level20;
wire [22:0] Add3Level20Wire = Add3Level20;

always @* begin
Add3Level20 = {AnswerLevel19, !Add1Level20Wire[60], 2'b0} + {AnswerLevel19, !Add1Level20Wire[60], 1'b0};
end

reg [43:0] Add4Level20;
wire [43:0] Add4Level20Wire = Add4Level20;

always @* begin
Add4Level20 = {PLevel19, 2'b0} - 3;
end

reg [43:0] Add5Level20;
wire [43:0] Add5Level20Wire = Add5Level20;

always @* begin
if(!Add1Level20Wire[60]) begin
Add5Level20 = Add4Level20Wire + Add2Level20Wire;
end
else begin
Add5Level20 = Add4Level20Wire - Add3Level20Wire;
end
end

reg [43:0] PLevel20;

always @(posedge clk) begin
PLevel20 end


// TwentyFirstst Level /////////////////////////////////////////////////////////////////////////////////////////////////////////

reg [63:0] Add1Level21;
wire [63:0] Add1Level21Wire = Add1Level21;

always @* begin
Add1Level21 = {2'b0, NumberLevel20[63:3]} - PLevel20;
end

reg [63:0] NumberLevel21;
reg [20:0] AnswerLevel21;

always @(posedge clk) begin
if(!Add1Level21Wire[63]) begin
NumberLevel21 end
else begin
NumberLevel21 end
AnswerLevel21 end

reg [25:0] Add2Level21;
wire [25:0] Add2Level21Wire = Add2Level21;

always @* begin
Add2Level21 = {AnswerLevel20, !Add1Level21Wire[63], 4'b0} + {AnswerLevel20, !Add1Level21Wire[63], 1'b0};
end

reg [23:0] Add3Level21;
wire [23:0] Add3Level21Wire = Add3Level21;

always @* begin
Add3Level21 = {AnswerLevel20, !Add1Level21Wire[63], 2'b0} + {AnswerLevel20, !Add1Level21Wire[63], 1'b0};
end

reg [45:0] Add4Level21;
wire [45:0] Add4Level21Wire = Add4Level21;

always @* begin
Add4Level21 = {PLevel20, 2'b0} - 3;
end

reg [45:0] Add5Level21;
wire [45:0] Add5Level21Wire = Add5Level21;

always @* begin
if(!Add1Level21Wire[63]) begin
Add5Level21 = Add4Level21Wire + Add2Level21Wire;
end
else begin
Add5Level21 = Add4Level21Wire - Add3Level21Wire;
end
end

reg [45:0] PLevel21;

always @(posedge clk) begin
PLevel21 end


// TwentySecondnd Level /////////////////////////////////////////////////////////////////////////////////////////////////////////

reg [66:0] Add1Level22;
wire [66:0] Add1Level22Wire = Add1Level22;

always @* begin
Add1Level22 = {2'b0, NumberLevel21} - PLevel21;
end

reg [63:0] NumberLevel22;
reg [21:0] AnswerLevel22;

always @(posedge clk) begin
if(!Add1Level22Wire[66]) begin
NumberLevel22 end
else begin
NumberLevel22 end
AnswerLevel22 end

assign Answer = AnswerLevel22;
assign Remainder = NumberLevel22;

endmodule

Testbench

`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 18:04:24 10/26/2013
// Design Name: CubeRoot
// Module Name: C:/Users/Siddarth/Documents/Xilinx/CubeRoot/CubeRootTest.v
// Project Name: CubeRoot
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: CubeRoot
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////

module CubeRootTest;

// Inputs
reg [63:0] Number;
reg clk;

// Outputs
wire [21:0] Answer;
wire [63:0] Remainder;
wire [63:0] NumberLevel1;
wire [63:0] NumberLevel2;
wire [63:0] NumberLevel3;
wire [63:0] NumberLevel4;
wire [63:0] NumberLevel5;
wire [63:0] NumberLevel6;
wire [63:0] NumberLevel7;
wire [63:0] NumberLevel8;
wire [63:0] NumberLevel9;
wire [63:0] NumberLevel10;


// Instantiate the Unit Under Test (UUT)
CubeRoot uut (
.Number(Number),
.clk(clk),
.Answer(Answer),
.Remainder(Remainder),
.NumberLevel1(NumberLevel1),
.NumberLevel2(NumberLevel2),
.NumberLevel3(NumberLevel3),
.NumberLevel4(NumberLevel4),
.NumberLevel5(NumberLevel5),
.NumberLevel6(NumberLevel6),
.NumberLevel7(NumberLevel7),
.NumberLevel8(NumberLevel8),
.NumberLevel9(NumberLevel9),
.NumberLevel10(NumberLevel10)
);

initial begin
// Initialize Inputs
Number = 0;
clk = 0;

// Wait 100 ns for global reset to finish
#100;

// Add stimulus here
Number = 27;
clk = 1;
#10;
clk = 0;
#10;
Number = 64;
clk = 1;
#10;
clk = 0;
#10;
Number = 216;
clk = 1;
#10;
clk = 0;
#10;
Number = 8;
clk = 1;
#10;
clk = 0;
#10;
Number = 125;
clk = 1;
#10;
clk = 0;
#10;
clk = 1;
#10;
clk = 0;
#10;
clk = 1;
#10;
clk = 0;
#10;
clk = 1;
#10;
clk = 0;
#10;
clk = 1;
#10;
clk = 0;
#10;
clk = 1;
#10;
clk = 0;
#10;
clk = 1;
#10;
clk = 0;
#10;
clk = 1;
#10;
clk = 0;
#10;
clk = 1;
#10;
clk = 0;
#10;
clk = 1;
#10;
clk = 0;
#10;
clk = 1;
#10;
clk = 0;
#10;
clk = 1;
#10;
clk = 0;
#10;
clk = 1;
#10;
clk = 0;
#10;
clk = 1;
#10;
clk = 0;
#10;
clk = 1;
#10;
clk = 0;
#10;
clk = 1;
#10;
clk = 0;
#10;
clk = 1;
#10;
clk = 0;
#10; clk = 1;
clk = 1;
#10;
clk = 0;
#10;
clk = 1;
#10;
clk = 0;
#10;
clk = 1;
#10;
clk = 0;
#10;
clk = 1;
#10;
clk = 0;
#10;
clk = 1;
#10;
clk = 0;
#10;
clk = 1;
#10;
clk = 0;
#10;
clk = 1;
#10;
clk = 0;
#10;
clk = 1;
#10;
clk = 0;
#10;
clk = 1;
#10;
clk = 0;
#10;
clk = 1;
#10;
clk = 0;
#10;
clk = 1;
#10;
clk = 0;
#10;
clk = 1;
#10;
clk = 0;
#10;
clk = 1;
#10;
clk = 0;
#10;
clk = 1;
#10;
clk = 0;
#10;
clk = 1;
#10;
clk = 0;
#10;
clk = 1;
#10;
clk = 0;
#10; clk = 1;



end


endmodule

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