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Iso7816_3_Master :: Overview

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Details

Name: iso7816_3_master
Created: Jan 9, 2011
Updated: Apr 18, 2011
SVN Updated: Apr 18, 2011
SVN: Browse
Latest version: download
Statistics: View

Other project properties

Category: Communication controller
Language: Verilog
Development status: Alpha
Additional info: FPGA proven
WishBone compliant: No
WishBone version: n/a
License: BSD

Description

This project aims at implementing a basic iso7816:3 master which can be controlled by software or by a state machine.
This is a work in progress. Currently, a draft implementation is being crafted just to identify the design challenges.
Once it is completed, the plan is to make a precise spec of a final version and then implement it.

Currently the IP supports only T=0, in direct and inverse convention. It does not handle T=0 parity error signaling / retry mechanism yet.

FPGA test included only the UART, not the master module.

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