Leros-32 :: Overview
Created: Mar 27, 2013
Updated: Apr 3, 2013
SVN: No files checked in
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Leros-32 is a 32-bit ALU port of the Leros project. It contains an icache and dcache implementation and interface for Xilinx based memory controller access. All of this can be realized inside of ~350 logic cells and 2 brams. This processor achieves > 100mhz running frequency inside of Spartan-6 hardware. A simple assembler is currently implemented and a port of binutils and llvm is in the works.
The processor core itself is an accumulator based design with an additional register for memory accesses. There are 256 pseudo registers which can be loaded or stored from the accumulator without touching the memory subsystem. All instructions except indirect load/store execute in a single cycle. Regular RISC 3 register codes can be emulated on this architecture using 3 operations. For example
add r0, r1, r2
could be translated to:
Such a technique is being explored for the LLVM port. In theory this should give leros about 1/3 the DMIPS/mhz as other much larger 32-bit cpus. However optimizations are often possible. For example the code a = b + c + d + e +f +g could be compiled into nearly the same number of instructions on leros-32 and ARM. Additionally, ARM may have several pipeline stalls to execute that code where as Leros-32 will have zero.
- 32-bit ALU
- 4GiB addressable memory
- Wishbone I/O Port
- Integral caches
- Extremely small logic footprint
- Single cycle execution of micro-ops
- Unified memory model
- Delay based simulation coding style
- High clock speed
- Assembler included
Leros-32 source is currently hosted at github.