LXP32, a lightweight 32-bit CPU core :: Overview
Other project properties
- described in portable VHDL-93, not tied to any particular vendor;
- 3-stage pipeline;
- 256 registers implemented as a RAM block;
- simple instruction set with less than 30 distinct opcodes;
- separate instruction and data buses, optional instruction cache;
- WISHBONE compatible;
- 8 interrupts with hardwired priorities;
- optional divider.
- synthesizable RTL description;
- automated verification environment (self-checking testbench);
- software tools (assembler/linker, disassembler) with source code.
LXP32 is distributed under the terms of the MIT license.