Serial Uart :: Overview
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Details
Name: miniuart2
Created: Jan 20, 2002
Updated: Aug 26, 2010
SVN Updated: May 6, 2009
SVN: Browse
Latest version: download
Statistics: View
Other project properties
Category: Communication controller
Language:
Development status: Mature
Additional info:
none
WishBone Compliant: Yes
License:
Description
Design in VHDL:
This UART is able to Transmit/Receive bytes in the configuration:
1 start bit - no parity - 1 stop bit.
It can be commanded by a microcontroller, or by other IP core.
It is not suited to interface a modem as there is no control handshaking (CTS/RTS).
It does'nt contain FIFO for emit/receive.
Features
• WISHBONE interface in 8-bit data bus
• Two clock: one for wishbone interface, one for RS232 bitstream generation
• Baudrate divisor from 1 to 65536 (generic parameter set at integration time)