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• Waterman, Jack

Overview

What it does:
This file computes the modulo-3 (%3) for a register which can range in size
from 3-bits to 64-bits. This is needed because most synthesis tools
(Xilinx XST) only deal with modulo's that are powers of 2, ie %2, %4, %8,
which of course are easy to do by looking at lsb's. You select your bitsize
in this file (modulo3_Nbit.v) and if you want to simulate, also select the
bitsize in file tb_modulo3.v. The other .v files are just for educational
purposes. The only file you need for your project is modulo3_Nbit.v

Why this is needed:
I needed a %3 for a 16-bit register in a project, so I came up with this
method. It is based on a theorem in math where in order to get the %3 of
any decimal number, you add up all the digits and take the %3 of the much
smaller number. For example, 2647347356834309872938763%3 = 1 because
2+6+4+7+...+7+6+3 = 127, and 127%3 = 10%3 = 1. There is another method to
do this: uses a multiplier to multiply the register by .33333 and keep only
the fractional part. But that is pretty unwieldy. However, if you know
your large registers are changing in a predictable manner, you can keep
track of your modulo-3 with a small counter starting from a known point.
This algorithm is for large registers changing in an unpredictable manner.

Simulation View: view_2m_sim_N_is_47.bmp
Enlarged Simulation View: view_enlarged_N_is_47.bmp

Disclaimer:
I have not formally proven the mathematics behind this project! I have
simulated many of the N's from 3 to 63 and my quick_check wire always stays
at zero. I am reasonably sure you can just take the modulo3_Nbit.v, change
the `define bitsize and the even/odd coding below that and you are done.
If you want more assurance, I suggest you simulate for your N for all inputs
to reg_to_solve for N less than, say, 24; and at least simulate for several
minutes for larger N.

Opencores.org, Jack Waterman and Compound Photonics are not liable for any
results concerning the use of this module. People who use this module
should only be professionals who are able to understand and assess the
impact of this module in their projects.

Please contact me with edits or bug concerns
- Jack Waterman, June 11, 2009
jack.waterman@compoundphotonics.com or 2258 S. Catarina Cir, Mesa AZ 85202.

modulo3_Nbit.v

//--------------------------------------------------------------------------
// Module : modulo3_Nbit
// Full Module Name : modulo3_Nbit.v
// Current Version : 1.0
// Version Date : June 8, 2009
//
// Description Modulo3 Combinational Calculation of 3 to 64-bit Registers
//
//
//--------------------------------------------------------------------------

`define bitsize 7'd47 // !!!

// VERY IMPORTANT VERY IMPORTANT VERY IMPORTANT VERY IMPORTANT
// VERY IMPORTANT: Search for !!! below and cover up the genvar h1 coding for
// the even or the odd 'bitsize.


// Project Comments
// This is the main comment block for the project, other files only have
// minimum comments. To use this file change the `define for bitsize above,
// and VERY IMPORTANT: cover up the coding below depending on whether bitsize
// is even or odd. (I could not think of a way to better do this.)
//
// What it does:
// This file computes the modulo-3 (%3) for a register which can range in size
// from 3-bits to 64-bits. This is needed because most synthesis tools
// (Xilinx XST) only deal with modulo's that are powers of 2, ie %2, %4, %8,
// which of course are easy to do by looking at lsb's. You select your bitsize
// in this file (modulo3_Nbit.v) and if you want to simulate, also select the
// bitsize in file tb_modulo3.v. The other .v files are just for educational
// purposes. The only file you need for your project is modulo3_Nbit.v
//
// Why this is needed:
// I needed a %3 for a 16-bit register in a project, so I came up with this
// method. It is based on a theorem in math where in order to get the %3 of
// any decimal number, you add up all the digits and take the %3 of the much
// smaller number. For example, 2647347356834309872938763%3 = 1 because
// 2+6+4+7+...+7+6+3 = 127, and 127%3 = 10%3 = 1. There is another method to
// do this: uses a multiplier to multiply the register by .33333 and keep only
// the fractional part. But that is pretty unwieldy. However, if you know
// your large registers are changing in a predictable manner, you can keep
// track of your modulo-3 with a small counter starting from a known point.
// This algorithm is for large registers changing in an unpredictable manner.
//
// Synthesis and Timing:
// I routed several different bitsize versions in Xilinx XST. XST does a good
// job of deleting all the unused upper bits above bitsize, which I merely
// zero out in the 'first_layer' processing. To check this, I compared
// routings of this file with bitsize set to 12, 13, 14, 15 and 36 against
// the .v files that I hand-edited to remove all the upper bits before
// synthesis. They all matched.
//
// The .ucf for the project was:
// NET "reg_to_solve*" TNM = ingrp;
// NET "result_mod3_*" TNM = outgrp;
// TIMESPEC TS01 = FROM ingrp TO outgrp 6 ns;
//
// I did a several routings to determine the maximum speed of the design for a
// few different bitsizes and virtex 5 speed grades.
// These delays do include I/O pads, which add of course adds additional delay.
// bit |lut |logic | virtex5 -1 | virtex5 -3
// size| | layers
// 4 2 2 5.718ns 4.680ns
// 8 5 3 6.721ns 5.339ns
// 12 10 4 7.176ns 5.364ns
// 13 10 4 7.059ns
// 14 13 4 7.935ns
// 15 12 4 7.773ns
// 16 14 4 8.412ns 5.597ns
// 31 28 5 8.927ns
// 32 30 5 8.578ns 6.423ns
// 36 34 6 9.503ns 7.148ns
// 47 44 6 9.640ns
// 48 46 6 9.295ns 7.520ns
// 63 60 6 10.103ns
// 64 62 6 9.737ns 7.814ns
//
//
// Of course, in your project this whole module will be placed between real
// registers and you should get your timing results directly in terms of your
// global clocks. The above chart just gives you an idea of the speed limits
// and LUT's used.
//
// Simulation:
// I made a testbench which tests this file (modulo3_Nbit.v) and also the
// hand-edited files for 12,13,14, 15 and 36 bits. For the hand-edited files
// I made a local counter to supply incremental input (reg_to_solve) so that I
// knew what the correct %3 answer would be. Then I made a 'quick_check' wire
// that compares the known %3 to the answer from this module. I ran the
// simulation in ModelSim and determined that the hand-edited files for 12,
// 13, 14 and 15 bits are perfect. The hand-edited version for 36 bits also
// looks perfect, but for 100% coverage the simulation would take 687 seconds.
// It takes me several minutes to simulate 100ms, so I decided to do something
// else. I created a 64-bit LFSR in the test bench (tb_modulo3.v)and used the
// lower 36 bitss for my input. Now, since I don't have a predictable input
// register, I used the RTL operator %3, which thankfully, ModelSim does well.
// I ran the simulation and the 'quick_check' wire is perfect for as long as I
// run the sim. Not 100% coverage; but good enough.
//
// I setup the simulation for the modulo3_Nbit.v with the LFSR as well. I
// included the test bench and the ModelSim sim.do and wave.do files so you can
// easily run this or edit it for your own simulator. I feel confident that
// you do not need to simulate this module, but if you do any editing beyond
// changing bitsize, I would recommend it. You can look at two bitmaps of my
// sim for bitsize = 47: view_2ms_sim_N_is_47.bmp and view_enlarged_N_is_47.bmp
// The sim is done by making a new ModelSim project, loading and compiling all
// eight .v files then just do commands: do sim.do, do wave.do and run 2ms
//
// Tools I used in this Project
// Xilinx 10.1 (freeware) on 32-bit Windows XP
// Mentor's ModelSim XEIII 6.3c (freeware, limited to Xilinx only, for their
// small to medium parts). Your ASIC or FPGA and simulator tool will need to
// do Verilog 2001 and be capable of doing "genvar" synthesis. If you don't
// have "genvar" you can always hand-edit for your specific bitsize need.
//
// Disclaimer:
// I have not formally proven the mathematics behind this project! I have
// simulated many of the N's from 3 to 63 and my quick_check wire always stays
// at zero. I am reasonably sure you can just take the modulo3_Nbit.v, change
// the `define bitsize and the even/odd coding below that and you are done.
// If you want more assurance, I suggest you simulate for your N for all inputs
// to reg_to_solve for N less than, say, 24; and at least simulate for several
// minutes for larger N.
//
// Opencores.org, Jack Waterman and Compound Photonics are not liable for any
// results concerning the use of this module. People who use this module
// should only be professionals who are able to understand and assess the
// impact of this module in their projects.
//
// Please contact me with edits or bug concerns
// - Jack Waterman, June 11, 2009
// jack.waterman@compoundphotonics.com or 2258 S. Catarina Cir, Mesa AZ 85202.



module modulo3_Nbit (
// inputs
reg_to_solve,

// outputs
result_mod3
);


//--------------------------------------------------------------------------
// Inputs / Outputs Description
//--------------------------------------------------------------------------

input [(`bitsize-1):0] reg_to_solve;
output [1:0] result_mod3;

//--------------------------------------------------------------------------
// Signal Declaration
//--------------------------------------------------------------------------

wire [63:0] first_layer;
reg [1:0] second_layer_3to0;
reg [1:0] second_layer_7to4;
reg [1:0] second_layer_11to8;
reg [1:0] second_layer_15to12;
reg [1:0] second_layer_19to16;
reg [1:0] second_layer_23to20;
reg [1:0] second_layer_27to24;
reg [1:0] second_layer_31to28;
reg [1:0] second_layer_35to32;
reg [1:0] second_layer_39to36;
reg [1:0] second_layer_43to40;
reg [1:0] second_layer_47to44;
reg [1:0] second_layer_51to48;
reg [1:0] second_layer_55to52;
reg [1:0] second_layer_59to56;
reg [1:0] second_layer_63to60;
reg [1:0] third_layer_7to0;
reg [1:0] third_layer_15to8;
reg [1:0] third_layer_23to16;
reg [1:0] third_layer_31to24;
reg [1:0] third_layer_39to32;
reg [1:0] third_layer_47to40;
reg [1:0] third_layer_55to48;
reg [1:0] third_layer_63to56;
reg [1:0] forth_layer_15to0;
reg [1:0] forth_layer_31to16;
reg [1:0] forth_layer_47to32;
reg [1:0] forth_layer_63to48;
reg [1:0] fifth_layer_31to0;
reg [1:0] fifth_layer_63to32;
reg [1:0] result_mod3;

// *****************************************************************
// Compute the modulo3 of reg_to_solve using combinational logic only
// *****************************************************************

//First examine the reg_to_solve pairs so that:
// 00 -> 00
// 01 -> 01
// 10 -> 10
// 11 -> 00


generate
genvar h;
for (h = 0; h <= (`bitsize-3); h = h + 2)
begin: xor_all_even_pairs
assign first_layer[h] = (reg_to_solve[h+1] ^ reg_to_solve[h]) & reg_to_solve[h];
assign first_layer[h+1] = (reg_to_solve[h+1] ^ reg_to_solve[h]) & reg_to_solve[h+1];
end
endgenerate

// VERY IMPORTANT VERY IMPORTANT VERY IMPORTANT VERY IMPORTANT VERY IMPORTANT VERY IMPORTANT
// ************** You Must Make a Choice !!! *****************************************************

// !!! Use this one for when 'bitsize is odd
generate
genvar h1;
for (h1 = (`bitsize-1); h1<=(`bitsize-1); h1 = h1+1)
begin: odd_without_xor
assign first_layer[h1] = reg_to_solve[h1];
end
endgenerate

// !!! Use this one for when 'bitsize is even
// generate
// genvar h1;
// for (h1 = (`bitsize-1); h1<=(`bitsize-1); h1 = h1+1)
// begin: last_xor
// assign first_layer[h1-1] = (reg_to_solve[h1] ^ reg_to_solve[h1-1]) & reg_to_solve[h1-1];
// assign first_layer[h1] = (reg_to_solve[h1] ^ reg_to_solve[h1-1]) & reg_to_solve[h1];
// end
// endgenerate
// **************************************************************************************************


generate
genvar h2;
for (h2 = (`bitsize); h2<=63; h2 = h2 + 1)
begin: zeroout_the_rest
assign first_layer[h2] = 1'b0;
end
endgenerate


always @ (first_layer)
begin
// nine choices:
// 0000 -> 00
// 0001 -> 01
// 0010 -> 10
// 0100 -> 01
// 0101 -> 10
// 0110 -> 00
// 1000 -> 10
// 1001 -> 00
// 1010 -> 01
case (first_layer[3:0])
4'b0000: begin
second_layer_3to0[1] = 1'b0;
second_layer_3to0[0] = 1'b0;
end
4'b0001: begin
second_layer_3to0[1] = 1'b0;
second_layer_3to0[0] = 1'b1;
end
4'b0010: begin
second_layer_3to0[1] = 1'b1;
second_layer_3to0[0] = 1'b0;
end
4'b0100: begin
second_layer_3to0[1] = 1'b0;
second_layer_3to0[0] = 1'b1;
end
4'b0101: begin
second_layer_3to0[1] = 1'b1;
second_layer_3to0[0] = 1'b0;
end
4'b0110: begin
second_layer_3to0[1] = 1'b0;
second_layer_3to0[0] = 1'b0;
end
4'b1000: begin
second_layer_3to0[1] = 1'b1;
second_layer_3to0[0] = 1'b0;
end
4'b1001: begin
second_layer_3to0[1] = 1'b0;
second_layer_3to0[0] = 1'b0;
end
4'b1010: begin
second_layer_3to0[1] = 1'b0;
second_layer_3to0[0] = 1'b1;
end
default: begin // Needed to prevent latches from being inferred
second_layer_3to0[1] = 1'b0;
second_layer_3to0[0] = 1'b0;
end
endcase

case (first_layer[7:4])
4'b0000:begin
second_layer_7to4[1] = 1'b0;
second_layer_7to4[0] = 1'b0;
end
4'b0001:begin
second_layer_7to4[1] = 1'b0;
second_layer_7to4[0] = 1'b1;
end
4'b0010:begin
second_layer_7to4[1] = 1'b1;
second_layer_7to4[0] = 1'b0;
end
4'b0100:begin
second_layer_7to4[1] = 1'b0;
second_layer_7to4[0] = 1'b1;
end
4'b0101:begin
second_layer_7to4[1] = 1'b1;
second_layer_7to4[0] = 1'b0;
end
4'b0110:begin
second_layer_7to4[1] = 1'b0;
second_layer_7to4[0] = 1'b0;
end
4'b1000:begin
second_layer_7to4[1] = 1'b1;
second_layer_7to4[0] = 1'b0;
end
4'b1001:begin
second_layer_7to4[1] = 1'b0;
second_layer_7to4[0] = 1'b0;
end
4'b1010:begin
second_layer_7to4[1] = 1'b0;
second_layer_7to4[0] = 1'b1;
end
default: begin // Needed to prevent latches from being inferred
second_layer_7to4[1] = 1'b0;
second_layer_7to4[0] = 1'b0;
end
endcase

case (first_layer[11:8])
4'b0000:begin
second_layer_11to8[1] = 1'b0;
second_layer_11to8[0] = 1'b0;
end
4'b0001:begin
second_layer_11to8[1] = 1'b0;
second_layer_11to8[0] = 1'b1;
end
4'b0010:begin
second_layer_11to8[1] = 1'b1;
second_layer_11to8[0] = 1'b0;
end
4'b0100:begin
second_layer_11to8[1] = 1'b0;
second_layer_11to8[0] = 1'b1;
end
4'b0101:begin
second_layer_11to8[1] = 1'b1;
second_layer_11to8[0] = 1'b0;
end
4'b0110:begin
second_layer_11to8[1] = 1'b0;
second_layer_11to8[0] = 1'b0;
end
4'b1000:begin
second_layer_11to8[1] = 1'b1;
second_layer_11to8[0] = 1'b0;
end
4'b1001:begin
second_layer_11to8[1] = 1'b0;
second_layer_11to8[0] = 1'b0;
end
4'b1010:begin
second_layer_11to8[1] = 1'b0;
second_layer_11to8[0] = 1'b1;
end
default: begin // Needed to prevent latches from being inferred
second_layer_11to8[1] = 1'b0;
second_layer_11to8[0] = 1'b0;
end
endcase

case (first_layer[15:12])
4'b0000:begin
second_layer_15to12[1] = 1'b0;
second_layer_15to12[0] = 1'b0;
end
4'b0001:begin
second_layer_15to12[1] = 1'b0;
second_layer_15to12[0] = 1'b1;
end
4'b0010:begin
second_layer_15to12[1] = 1'b1;
second_layer_15to12[0] = 1'b0;
end
4'b0100:begin
second_layer_15to12[1] = 1'b0;
second_layer_15to12[0] = 1'b1;
end
4'b0101:begin
second_layer_15to12[1] = 1'b1;
second_layer_15to12[0] = 1'b0;
end
4'b0110:begin
second_layer_15to12[1] = 1'b0;
second_layer_15to12[0] = 1'b0;
end
4'b1000:begin
second_layer_15to12[1] = 1'b1;
second_layer_15to12[0] = 1'b0;
end
4'b1001:begin
second_layer_15to12[1] = 1'b0;
second_layer_15to12[0] = 1'b0;
end
4'b1010:begin
second_layer_15to12[1] = 1'b0;
second_layer_15to12[0] = 1'b1;
end
default: begin // Needed to prevent latches from being inferred
second_layer_15to12[1] = 1'b0;
second_layer_15to12[0] = 1'b0;
end
endcase

case (first_layer[19:16])
4'b0000:begin
second_layer_19to16[1] = 1'b0;
second_layer_19to16[0] = 1'b0;
end
4'b0001:begin
second_layer_19to16[1] = 1'b0;
second_layer_19to16[0] = 1'b1;
end
4'b0010:begin
second_layer_19to16[1] = 1'b1;
second_layer_19to16[0] = 1'b0;
end
4'b0100:begin
second_layer_19to16[1] = 1'b0;
second_layer_19to16[0] = 1'b1;
end
4'b0101:begin
second_layer_19to16[1] = 1'b1;
second_layer_19to16[0] = 1'b0;
end
4'b0110:begin
second_layer_19to16[1] = 1'b0;
second_layer_19to16[0] = 1'b0;
end
4'b1000:begin
second_layer_19to16[1] = 1'b1;
second_layer_19to16[0] = 1'b0;
end
4'b1001:begin
second_layer_19to16[1] = 1'b0;
second_layer_19to16[0] = 1'b0;
end
4'b1010:begin
second_layer_19to16[1] = 1'b0;
second_layer_19to16[0] = 1'b1;
end
default: begin // Needed to prevent latches from being inferred
second_layer_19to16[1] = 1'b0;
second_layer_19to16[0] = 1'b0;
end
endcase

case (first_layer[23:20])
4'b0000:begin
second_layer_23to20[1] = 1'b0;
second_layer_23to20[0] = 1'b0;
end
4'b0001:begin
second_layer_23to20[1] = 1'b0;
second_layer_23to20[0] = 1'b1;
end
4'b0010:begin
second_layer_23to20[1] = 1'b1;
second_layer_23to20[0] = 1'b0;
end
4'b0100:begin
second_layer_23to20[1] = 1'b0;
second_layer_23to20[0] = 1'b1;
end
4'b0101:begin
second_layer_23to20[1] = 1'b1;
second_layer_23to20[0] = 1'b0;
end
4'b0110:begin
second_layer_23to20[1] = 1'b0;
second_layer_23to20[0] = 1'b0;
end
4'b1000:begin
second_layer_23to20[1] = 1'b1;
second_layer_23to20[0] = 1'b0;
end
4'b1001:begin
second_layer_23to20[1] = 1'b0;
second_layer_23to20[0] = 1'b0;
end
4'b1010:begin
second_layer_23to20[1] = 1'b0;
second_layer_23to20[0] = 1'b1;
end
default: begin // Needed to prevent latches from being inferred
second_layer_23to20[1] = 1'b0;
second_layer_23to20[0] = 1'b0;
end
endcase

case (first_layer[27:24])
4'b0000:begin
second_layer_27to24[1] = 1'b0;
second_layer_27to24[0] = 1'b0;
end
4'b0001:begin
second_layer_27to24[1] = 1'b0;
second_layer_27to24[0] = 1'b1;
end
4'b0010:begin
second_layer_27to24[1] = 1'b1;
second_layer_27to24[0] = 1'b0;
end
4'b0100:begin
second_layer_27to24[1] = 1'b0;
second_layer_27to24[0] = 1'b1;
end
4'b0101:begin
second_layer_27to24[1] = 1'b1;
second_layer_27to24[0] = 1'b0;
end
4'b0110:begin
second_layer_27to24[1] = 1'b0;
second_layer_27to24[0] = 1'b0;
end
4'b1000:begin
second_layer_27to24[1] = 1'b1;
second_layer_27to24[0] = 1'b0;
end
4'b1001:begin
second_layer_27to24[1] = 1'b0;
second_layer_27to24[0] = 1'b0;
end
4'b1010:begin
second_layer_27to24[1] = 1'b0;
second_layer_27to24[0] = 1'b1;
end
default: begin // Needed to prevent latches from being inferred
second_layer_27to24[1] = 1'b0;
second_layer_27to24[0] = 1'b0;
end
endcase

case (first_layer[31:28])
4'b0000:begin
second_layer_31to28[1] = 1'b0;
second_layer_31to28[0] = 1'b0;
end
4'b0001:begin
second_layer_31to28[1] = 1'b0;
second_layer_31to28[0] = 1'b1;
end
4'b0010:begin
second_layer_31to28[1] = 1'b1;
second_layer_31to28[0] = 1'b0;
end
4'b0100:begin
second_layer_31to28[1] = 1'b0;
second_layer_31to28[0] = 1'b1;
end
4'b0101:begin
second_layer_31to28[1] = 1'b1;
second_layer_31to28[0] = 1'b0;
end
4'b0110:begin
second_layer_31to28[1] = 1'b0;
second_layer_31to28[0] = 1'b0;
end
4'b1000:begin
second_layer_31to28[1] = 1'b1;
second_layer_31to28[0] = 1'b0;
end
4'b1001:begin
second_layer_31to28[1] = 1'b0;
second_layer_31to28[0] = 1'b0;
end
4'b1010:begin
second_layer_31to28[1] = 1'b0;
second_layer_31to28[0] = 1'b1;
end
default: begin // Needed to prevent latches from being inferred
second_layer_31to28[1] = 1'b0;
second_layer_31to28[0] = 1'b0;
end
endcase

case (first_layer[35:32])
4'b0000:begin
second_layer_35to32[1] = 1'b0;
second_layer_35to32[0] = 1'b0;
end
4'b0001:begin
second_layer_35to32[1] = 1'b0;
second_layer_35to32[0] = 1'b1;
end
4'b0010:begin
second_layer_35to32[1] = 1'b1;
second_layer_35to32[0] = 1'b0;
end
4'b0100:begin
second_layer_35to32[1] = 1'b0;
second_layer_35to32[0] = 1'b1;
end
4'b0101:begin
second_layer_35to32[1] = 1'b1;
second_layer_35to32[0] = 1'b0;
end
4'b0110:begin
second_layer_35to32[1] = 1'b0;
second_layer_35to32[0] = 1'b0;
end
4'b1000:begin
second_layer_35to32[1] = 1'b1;
second_layer_35to32[0] = 1'b0;
end
4'b1001:begin
second_layer_35to32[1] = 1'b0;
second_layer_35to32[0] = 1'b0;
end
4'b1010:begin
second_layer_35to32[1] = 1'b0;
second_layer_35to32[0] = 1'b1;
end
default: begin // Needed to prevent latches from being inferred
second_layer_35to32[1] = 1'b0;
second_layer_35to32[0] = 1'b0;
end
endcase

case (first_layer[39:36])
4'b0000:begin
second_layer_39to36[1] = 1'b0;
second_layer_39to36[0] = 1'b0;
end
4'b0001:begin
second_layer_39to36[1] = 1'b0;
second_layer_39to36[0] = 1'b1;
end
4'b0010:begin
second_layer_39to36[1] = 1'b1;
second_layer_39to36[0] = 1'b0;
end
4'b0100:begin
second_layer_39to36[1] = 1'b0;
second_layer_39to36[0] = 1'b1;
end
4'b0101:begin
second_layer_39to36[1] = 1'b1;
second_layer_39to36[0] = 1'b0;
end
4'b0110:begin
second_layer_39to36[1] = 1'b0;
second_layer_39to36[0] = 1'b0;
end
4'b1000:begin
second_layer_39to36[1] = 1'b1;
second_layer_39to36[0] = 1'b0;
end
4'b1001:begin
second_layer_39to36[1] = 1'b0;
second_layer_39to36[0] = 1'b0;
end
4'b1010:begin
second_layer_39to36[1] = 1'b0;
second_layer_39to36[0] = 1'b1;
end
default: begin // Needed to prevent latches from being inferred
second_layer_39to36[1] = 1'b0;
second_layer_39to36[0] = 1'b0;
end
endcase

case (first_layer[43:40])
4'b0000:begin
second_layer_43to40[1] = 1'b0;
second_layer_43to40[0] = 1'b0;
end
4'b0001:begin
second_layer_43to40[1] = 1'b0;
second_layer_43to40[0] = 1'b1;
end
4'b0010:begin
second_layer_43to40[1] = 1'b1;
second_layer_43to40[0] = 1'b0;
end
4'b0100:begin
second_layer_43to40[1] = 1'b0;
second_layer_43to40[0] = 1'b1;
end
4'b0101:begin
second_layer_43to40[1] = 1'b1;
second_layer_43to40[0] = 1'b0;
end
4'b0110:begin
second_layer_43to40[1] = 1'b0;
second_layer_43to40[0] = 1'b0;
end
4'b1000:begin
second_layer_43to40[1] = 1'b1;
second_layer_43to40[0] = 1'b0;
end
4'b1001:begin
second_layer_43to40[1] = 1'b0;
second_layer_43to40[0] = 1'b0;
end
4'b1010:begin
second_layer_43to40[1] = 1'b0;
second_layer_43to40[0] = 1'b1;
end
default: begin // Needed to prevent latches from being inferred
second_layer_43to40[1] = 1'b0;
second_layer_43to40[0] = 1'b0;
end
endcase

case (first_layer[47:44])
4'b0000:begin
second_layer_47to44[1] = 1'b0;
second_layer_47to44[0] = 1'b0;
end
4'b0001:begin
second_layer_47to44[1] = 1'b0;
second_layer_47to44[0] = 1'b1;
end
4'b0010:begin
second_layer_47to44[1] = 1'b1;
second_layer_47to44[0] = 1'b0;
end
4'b0100:begin
second_layer_47to44[1] = 1'b0;
second_layer_47to44[0] = 1'b1;
end
4'b0101:begin
second_layer_47to44[1] = 1'b1;
second_layer_47to44[0] = 1'b0;
end
4'b0110:begin
second_layer_47to44[1] = 1'b0;
second_layer_47to44[0] = 1'b0;
end
4'b1000:begin
second_layer_47to44[1] = 1'b1;
second_layer_47to44[0] = 1'b0;
end
4'b1001:begin
second_layer_47to44[1] = 1'b0;
second_layer_47to44[0] = 1'b0;
end
4'b1010:begin
second_layer_47to44[1] = 1'b0;
second_layer_47to44[0] = 1'b1;
end
default: begin // Needed to prevent latches from being inferred
second_layer_47to44[1] = 1'b0;
second_layer_47to44[0] = 1'b0;
end
endcase

case (first_layer[51:48])
4'b0000:begin
second_layer_51to48[1] = 1'b0;
second_layer_51to48[0] = 1'b0;
end
4'b0001:begin
second_layer_51to48[1] = 1'b0;
second_layer_51to48[0] = 1'b1;
end
4'b0010:begin
second_layer_51to48[1] = 1'b1;
second_layer_51to48[0] = 1'b0;
end
4'b0100:begin
second_layer_51to48[1] = 1'b0;
second_layer_51to48[0] = 1'b1;
end
4'b0101:begin
second_layer_51to48[1] = 1'b1;
second_layer_51to48[0] = 1'b0;
end
4'b0110:begin
second_layer_51to48[1] = 1'b0;
second_layer_51to48[0] = 1'b0;
end
4'b1000:begin
second_layer_51to48[1] = 1'b1;
second_layer_51to48[0] = 1'b0;
end
4'b1001:begin
second_layer_51to48[1] = 1'b0;
second_layer_51to48[0] = 1'b0;
end
4'b1010:begin
second_layer_51to48[1] = 1'b0;
second_layer_51to48[0] = 1'b1;
end
default: begin // Needed to prevent latches from being inferred
second_layer_51to48[1] = 1'b0;
second_layer_51to48[0] = 1'b0;
end
endcase

case (first_layer[55:52])
4'b0000:begin
second_layer_55to52[1] = 1'b0;
second_layer_55to52[0] = 1'b0;
end
4'b0001:begin
second_layer_55to52[1] = 1'b0;
second_layer_55to52[0] = 1'b1;
end
4'b0010:begin
second_layer_55to52[1] = 1'b1;
second_layer_55to52[0] = 1'b0;
end
4'b0100:begin
second_layer_55to52[1] = 1'b0;
second_layer_55to52[0] = 1'b1;
end
4'b0101:begin
second_layer_55to52[1] = 1'b1;
second_layer_55to52[0] = 1'b0;
end
4'b0110:begin
second_layer_55to52[1] = 1'b0;
second_layer_55to52[0] = 1'b0;
end
4'b1000:begin
second_layer_55to52[1] = 1'b1;
second_layer_55to52[0] = 1'b0;
end
4'b1001:begin
second_layer_55to52[1] = 1'b0;
second_layer_55to52[0] = 1'b0;
end
4'b1010:begin
second_layer_55to52[1] = 1'b0;
second_layer_55to52[0] = 1'b1;
end
default: begin // Needed to prevent latches from being inferred
second_layer_55to52[1] = 1'b0;
second_layer_55to52[0] = 1'b0;
end
endcase

case (first_layer[59:56])
4'b0000:begin
second_layer_59to56[1] = 1'b0;
second_layer_59to56[0] = 1'b0;
end
4'b0001:begin
second_layer_59to56[1] = 1'b0;
second_layer_59to56[0] = 1'b1;
end
4'b0010:begin
second_layer_59to56[1] = 1'b1;
second_layer_59to56[0] = 1'b0;
end
4'b0100:begin
second_layer_59to56[1] = 1'b0;
second_layer_59to56[0] = 1'b1;
end
4'b0101:begin
second_layer_59to56[1] = 1'b1;
second_layer_59to56[0] = 1'b0;
end
4'b0110:begin
second_layer_59to56[1] = 1'b0;
second_layer_59to56[0] = 1'b0;
end
4'b1000:begin
second_layer_59to56[1] = 1'b1;
second_layer_59to56[0] = 1'b0;
end
4'b1001:begin
second_layer_59to56[1] = 1'b0;
second_layer_59to56[0] = 1'b0;
end
4'b1010:begin
second_layer_59to56[1] = 1'b0;
second_layer_59to56[0] = 1'b1;
end
default: begin // Needed to prevent latches from being inferred
second_layer_59to56[1] = 1'b0;
second_layer_59to56[0] = 1'b0;
end
endcase

case (first_layer[63:60])
4'b0000:begin
second_layer_63to60[1] = 1'b0;
second_layer_63to60[0] = 1'b0;
end
4'b0001:begin
second_layer_63to60[1] = 1'b0;
second_layer_63to60[0] = 1'b1;
end
4'b0010:begin
second_layer_63to60[1] = 1'b1;
second_layer_63to60[0] = 1'b0;
end
4'b0100:begin
second_layer_63to60[1] = 1'b0;
second_layer_63to60[0] = 1'b1;
end
4'b0101:begin
second_layer_63to60[1] = 1'b1;
second_layer_63to60[0] = 1'b0;
end
4'b0110:begin
second_layer_63to60[1] = 1'b0;
second_layer_63to60[0] = 1'b0;
end
4'b1000:begin
second_layer_63to60[1] = 1'b1;
second_layer_63to60[0] = 1'b0;
end
4'b1001:begin
second_layer_63to60[1] = 1'b0;
second_layer_63to60[0] = 1'b0;
end
4'b1010:begin
second_layer_63to60[1] = 1'b0;
second_layer_63to60[0] = 1'b1;
end
default: begin // Needed to prevent latches from being inferred
second_layer_63to60[1] = 1'b0;
second_layer_63to60[0] = 1'b0;
end
endcase
end //always



always @ (second_layer_7to4 or second_layer_3to0)
begin
case ({second_layer_7to4[1:0],second_layer_3to0[1:0]})
4'b0000:begin
third_layer_7to0[1] = 1'b0;
third_layer_7to0[0] = 1'b0;
end
4'b0001:begin
third_layer_7to0[1] = 1'b0;
third_layer_7to0[0] = 1'b1;
end
4'b0010:begin
third_layer_7to0[1] = 1'b1;
third_layer_7to0[0] = 1'b0;
end
4'b0100:begin
third_layer_7to0[1] = 1'b0;
third_layer_7to0[0] = 1'b1;
end
4'b0101:begin
third_layer_7to0[1] = 1'b1;
third_layer_7to0[0] = 1'b0;
end
4'b0110:begin
third_layer_7to0[1] = 1'b0;
third_layer_7to0[0] = 1'b0;
end
4'b1000:begin
third_layer_7to0[1] = 1'b1;
third_layer_7to0[0] = 1'b0;
end
4'b1001:begin
third_layer_7to0[1] = 1'b0;
third_layer_7to0[0] = 1'b0;
end
4'b1010:begin
third_layer_7to0[1] = 1'b0;
third_layer_7to0[0] = 1'b1;
end
default: begin // Needed to prevent latches from being inferred
third_layer_7to0[1] = 1'b0;
third_layer_7to0[0] = 1'b0;
end
endcase
end // always

always @ (second_layer_15to12 or second_layer_11to8)
begin

case ({second_layer_15to12[1:0],second_layer_11to8[1:0]})
4'b0000:begin
third_layer_15to8[1] = 1'b0;
third_layer_15to8[0] = 1'b0;
end
4'b0001:begin
third_layer_15to8[1] = 1'b0;
third_layer_15to8[0] = 1'b1;
end
4'b0010:begin
third_layer_15to8[1] = 1'b1;
third_layer_15to8[0] = 1'b0;
end
4'b0100:begin
third_layer_15to8[1] = 1'b0;
third_layer_15to8[0] = 1'b1;
end
4'b0101:begin
third_layer_15to8[1] = 1'b1;
third_layer_15to8[0] = 1'b0;
end
4'b0110:begin
third_layer_15to8[1] = 1'b0;
third_layer_15to8[0] = 1'b0;
end
4'b1000:begin
third_layer_15to8[1] = 1'b1;
third_layer_15to8[0] = 1'b0;
end
4'b1001:begin
third_layer_15to8[1] = 1'b0;
third_layer_15to8[0] = 1'b0;
end
4'b1010:begin
third_layer_15to8[1] = 1'b0;
third_layer_15to8[0] = 1'b1;
end
default: begin // Needed to prevent latches from being inferred
third_layer_15to8[1] = 1'b0;
third_layer_15to8[0] = 1'b0;
end
endcase
end // always


always @ (second_layer_23to20 or second_layer_19to16)
begin

case ({second_layer_23to20[1:0],second_layer_19to16[1:0]})
4'b0000:begin
third_layer_23to16[1] = 1'b0;
third_layer_23to16[0] = 1'b0;
end
4'b0001:begin
third_layer_23to16[1] = 1'b0;
third_layer_23to16[0] = 1'b1;
end
4'b0010:begin
third_layer_23to16[1] = 1'b1;
third_layer_23to16[0] = 1'b0;
end
4'b0100:begin
third_layer_23to16[1] = 1'b0;
third_layer_23to16[0] = 1'b1;
end
4'b0101:begin
third_layer_23to16[1] = 1'b1;
third_layer_23to16[0] = 1'b0;
end
4'b0110:begin
third_layer_23to16[1] = 1'b0;
third_layer_23to16[0] = 1'b0;
end
4'b1000:begin
third_layer_23to16[1] = 1'b1;
third_layer_23to16[0] = 1'b0;
end
4'b1001:begin
third_layer_23to16[1] = 1'b0;
third_layer_23to16[0] = 1'b0;
end
4'b1010:begin
third_layer_23to16[1] = 1'b0;
third_layer_23to16[0] = 1'b1;
end
default: begin // Needed to prevent latches from being inferred
third_layer_23to16[1] = 1'b0;
third_layer_23to16[0] = 1'b0;
end
endcase
end // always



always @ (second_layer_31to28 or second_layer_27to24)
begin

case ({second_layer_31to28[1:0],second_layer_27to24[1:0]})
4'b0000:begin
third_layer_31to24[1] = 1'b0;
third_layer_31to24[0] = 1'b0;
end
4'b0001:begin
third_layer_31to24[1] = 1'b0;
third_layer_31to24[0] = 1'b1;
end
4'b0010:begin
third_layer_31to24[1] = 1'b1;
third_layer_31to24[0] = 1'b0;
end
4'b0100:begin
third_layer_31to24[1] = 1'b0;
third_layer_31to24[0] = 1'b1;
end
4'b0101:begin
third_layer_31to24[1] = 1'b1;
third_layer_31to24[0] = 1'b0;
end
4'b0110:begin
third_layer_31to24[1] = 1'b0;
third_layer_31to24[0] = 1'b0;
end
4'b1000:begin
third_layer_31to24[1] = 1'b1;
third_layer_31to24[0] = 1'b0;
end
4'b1001:begin
third_layer_31to24[1] = 1'b0;
third_layer_31to24[0] = 1'b0;
end
4'b1010:begin
third_layer_31to24[1] = 1'b0;
third_layer_31to24[0] = 1'b1;
end
default: begin // Needed to prevent latches from being inferred
third_layer_31to24[1] = 1'b0;
third_layer_31to24[0] = 1'b0;
end
endcase
end // always


always @ (second_layer_39to36 or second_layer_35to32)
begin

case ({second_layer_39to36[1:0],second_layer_35to32[1:0]})
4'b0000:begin
third_layer_39to32[1] = 1'b0;
third_layer_39to32[0] = 1'b0;
end
4'b0001:begin
third_layer_39to32[1] = 1'b0;
third_layer_39to32[0] = 1'b1;
end
4'b0010:begin
third_layer_39to32[1] = 1'b1;
third_layer_39to32[0] = 1'b0;
end
4'b0100:begin
third_layer_39to32[1] = 1'b0;
third_layer_39to32[0] = 1'b1;
end
4'b0101:begin
third_layer_39to32[1] = 1'b1;
third_layer_39to32[0] = 1'b0;
end
4'b0110:begin
third_layer_39to32[1] = 1'b0;
third_layer_39to32[0] = 1'b0;
end
4'b1000:begin
third_layer_39to32[1] = 1'b1;
third_layer_39to32[0] = 1'b0;
end
4'b1001:begin
third_layer_39to32[1] = 1'b0;
third_layer_39to32[0] = 1'b0;
end
4'b1010:begin
third_layer_39to32[1] = 1'b0;
third_layer_39to32[0] = 1'b1;
end
default: begin // Needed to prevent latches from being inferred
third_layer_39to32[1] = 1'b0;
third_layer_39to32[0] = 1'b0;
end
endcase
end // always


always @ (second_layer_47to44 or second_layer_43to40)
begin

case ({second_layer_47to44[1:0],second_layer_43to40[1:0]})
4'b0000:begin
third_layer_47to40[1] = 1'b0;
third_layer_47to40[0] = 1'b0;
end
4'b0001:begin
third_layer_47to40[1] = 1'b0;
third_layer_47to40[0] = 1'b1;
end
4'b0010:begin
third_layer_47to40[1] = 1'b1;
third_layer_47to40[0] = 1'b0;
end
4'b0100:begin
third_layer_47to40[1] = 1'b0;
third_layer_47to40[0] = 1'b1;
end
4'b0101:begin
third_layer_47to40[1] = 1'b1;
third_layer_47to40[0] = 1'b0;
end
4'b0110:begin
third_layer_47to40[1] = 1'b0;
third_layer_47to40[0] = 1'b0;
end
4'b1000:begin
third_layer_47to40[1] = 1'b1;
third_layer_47to40[0] = 1'b0;
end
4'b1001:begin
third_layer_47to40[1] = 1'b0;
third_layer_47to40[0] = 1'b0;
end
4'b1010:begin
third_layer_47to40[1] = 1'b0;
third_layer_47to40[0] = 1'b1;
end
default: begin // Needed to prevent latches from being inferred
third_layer_47to40[1] = 1'b0;
third_layer_47to40[0] = 1'b0;
end
endcase
end // always


always @ (second_layer_55to52 or second_layer_51to48)
begin

case ({second_layer_55to52[1:0],second_layer_51to48[1:0]})
4'b0000:begin
third_layer_55to48[1] = 1'b0;
third_layer_55to48[0] = 1'b0;
end
4'b0001:begin
third_layer_55to48[1] = 1'b0;
third_layer_55to48[0] = 1'b1;
end
4'b0010:begin
third_layer_55to48[1] = 1'b1;
third_layer_55to48[0] = 1'b0;
end
4'b0100:begin
third_layer_55to48[1] = 1'b0;
third_layer_55to48[0] = 1'b1;
end
4'b0101:begin
third_layer_55to48[1] = 1'b1;
third_layer_55to48[0] = 1'b0;
end
4'b0110:begin
third_layer_55to48[1] = 1'b0;
third_layer_55to48[0] = 1'b0;
end
4'b1000:begin
third_layer_55to48[1] = 1'b1;
third_layer_55to48[0] = 1'b0;
end
4'b1001:begin
third_layer_55to48[1] = 1'b0;
third_layer_55to48[0] = 1'b0;
end
4'b1010:begin
third_layer_55to48[1] = 1'b0;
third_layer_55to48[0] = 1'b1;
end
default: begin // Needed to prevent latches from being inferred
third_layer_55to48[1] = 1'b0;
third_layer_55to48[0] = 1'b0;
end
endcase
end // always


always @ (second_layer_63to60 or second_layer_59to56)
begin

case ({second_layer_63to60[1:0],second_layer_59to56[1:0]})
4'b0000:begin
third_layer_63to56[1] = 1'b0;
third_layer_63to56[0] = 1'b0;
end
4'b0001:begin
third_layer_63to56[1] = 1'b0;
third_layer_63to56[0] = 1'b1;
end
4'b0010:begin
third_layer_63to56[1] = 1'b1;
third_layer_63to56[0] = 1'b0;
end
4'b0100:begin
third_layer_63to56[1] = 1'b0;
third_layer_63to56[0] = 1'b1;
end
4'b0101:begin
third_layer_63to56[1] = 1'b1;
third_layer_63to56[0] = 1'b0;
end
4'b0110:begin
third_layer_63to56[1] = 1'b0;
third_layer_63to56[0] = 1'b0;
end
4'b1000:begin
third_layer_63to56[1] = 1'b1;
third_layer_63to56[0] = 1'b0;
end
4'b1001:begin
third_layer_63to56[1] = 1'b0;
third_layer_63to56[0] = 1'b0;
end
4'b1010:begin
third_layer_63to56[1] = 1'b0;
third_layer_63to56[0] = 1'b1;
end
default: begin // Needed to prevent latches from being inferred
third_layer_63to56[1] = 1'b0;
third_layer_63to56[0] = 1'b0;
end
endcase
end // always


always @ (third_layer_15to8 or third_layer_7to0)
begin

case ({third_layer_15to8[1:0],third_layer_7to0[1:0]})
4'b0000:begin
forth_layer_15to0[1] = 1'b0;
forth_layer_15to0[0] = 1'b0;
end
4'b0001:begin
forth_layer_15to0[1] = 1'b0;
forth_layer_15to0[0] = 1'b1;
end
4'b0010:begin
forth_layer_15to0[1] = 1'b1;
forth_layer_15to0[0] = 1'b0;
end
4'b0100:begin
forth_layer_15to0[1] = 1'b0;
forth_layer_15to0[0] = 1'b1;
end
4'b0101:begin
forth_layer_15to0[1] = 1'b1;
forth_layer_15to0[0] = 1'b0;
end
4'b0110:begin
forth_layer_15to0[1] = 1'b0;
forth_layer_15to0[0] = 1'b0;
end
4'b1000:begin
forth_layer_15to0[1] = 1'b1;
forth_layer_15to0[0] = 1'b0;
end
4'b1001:begin
forth_layer_15to0[1] = 1'b0;
forth_layer_15to0[0] = 1'b0;
end
4'b1010:begin
forth_layer_15to0[1] = 1'b0;
forth_layer_15to0[0] = 1'b1;
end
default: begin // Needed to prevent latches from being inferred
forth_layer_15to0[1] = 1'b0;
forth_layer_15to0[0] = 1'b0;
end
endcase
end // always


always @ (third_layer_31to24 or third_layer_23to16)
begin

case ({third_layer_31to24[1:0],third_layer_23to16[1:0]})
4'b0000:begin
forth_layer_31to16[1] = 1'b0;
forth_layer_31to16[0] = 1'b0;
end
4'b0001:begin
forth_layer_31to16[1] = 1'b0;
forth_layer_31to16[0] = 1'b1;
end
4'b0010:begin
forth_layer_31to16[1] = 1'b1;
forth_layer_31to16[0] = 1'b0;
end
4'b0100:begin
forth_layer_31to16[1] = 1'b0;
forth_layer_31to16[0] = 1'b1;
end
4'b0101:begin
forth_layer_31to16[1] = 1'b1;
forth_layer_31to16[0] = 1'b0;
end
4'b0110:begin
forth_layer_31to16[1] = 1'b0;
forth_layer_31to16[0] = 1'b0;
end
4'b1000:begin
forth_layer_31to16[1] = 1'b1;
forth_layer_31to16[0] = 1'b0;
end
4'b1001:begin
forth_layer_31to16[1] = 1'b0;
forth_layer_31to16[0] = 1'b0;
end
4'b1010:begin
forth_layer_31to16[1] = 1'b0;
forth_layer_31to16[0] = 1'b1;
end
default: begin // Needed to prevent latches from being inferred
forth_layer_31to16[1] = 1'b0;
forth_layer_31to16[0] = 1'b0;
end
endcase
end // always

always @ (third_layer_47to40 or third_layer_39to32)
begin

case ({third_layer_47to40[1:0],third_layer_39to32[1:0]})
4'b0000:begin
forth_layer_47to32[1] = 1'b0;
forth_layer_47to32[0] = 1'b0;
end
4'b0001:begin
forth_layer_47to32[1] = 1'b0;
forth_layer_47to32[0] = 1'b1;
end
4'b0010:begin
forth_layer_47to32[1] = 1'b1;
forth_layer_47to32[0] = 1'b0;
end
4'b0100:begin
forth_layer_47to32[1] = 1'b0;
forth_layer_47to32[0] = 1'b1;
end
4'b0101:begin
forth_layer_47to32[1] = 1'b1;
forth_layer_47to32[0] = 1'b0;
end
4'b0110:begin
forth_layer_47to32[1] = 1'b0;
forth_layer_47to32[0] = 1'b0;
end
4'b1000:begin
forth_layer_47to32[1] = 1'b1;
forth_layer_47to32[0] = 1'b0;
end
4'b1001:begin
forth_layer_47to32[1] = 1'b0;
forth_layer_47to32[0] = 1'b0;
end
4'b1010:begin
forth_layer_47to32[1] = 1'b0;
forth_layer_47to32[0] = 1'b1;
end
default: begin // Needed to prevent latches from being inferred
forth_layer_47to32[1] = 1'b0;
forth_layer_47to32[0] = 1'b0;
end
endcase
end // always


always @ (third_layer_63to56 or third_layer_55to48)
begin

case ({third_layer_63to56[1:0],third_layer_55to48[1:0]})
4'b0000:begin
forth_layer_63to48[1] = 1'b0;
forth_layer_63to48[0] = 1'b0;
end
4'b0001:begin
forth_layer_63to48[1] = 1'b0;
forth_layer_63to48[0] = 1'b1;
end
4'b0010:begin
forth_layer_63to48[1] = 1'b1;
forth_layer_63to48[0] = 1'b0;
end
4'b0100:begin
forth_layer_63to48[1] = 1'b0;
forth_layer_63to48[0] = 1'b1;
end
4'b0101:begin
forth_layer_63to48[1] = 1'b1;
forth_layer_63to48[0] = 1'b0;
end
4'b0110:begin
forth_layer_63to48[1] = 1'b0;
forth_layer_63to48[0] = 1'b0;
end
4'b1000:begin
forth_layer_63to48[1] = 1'b1;
forth_layer_63to48[0] = 1'b0;
end
4'b1001:begin
forth_layer_63to48[1] = 1'b0;
forth_layer_63to48[0] = 1'b0;
end
4'b1010:begin
forth_layer_63to48[1] = 1'b0;
forth_layer_63to48[0] = 1'b1;
end
default: begin // Needed to prevent latches from being inferred
forth_layer_63to48[1] = 1'b0;
forth_layer_63to48[0] = 1'b0;
end
endcase
end // always


always @ (forth_layer_31to16 or forth_layer_15to0)
begin

case ({forth_layer_31to16[1:0],forth_layer_15to0[1:0]})
4'b0000:begin
fifth_layer_31to0[1] = 1'b0;
fifth_layer_31to0[0] = 1'b0;
end
4'b0001:begin
fifth_layer_31to0[1] = 1'b0;
fifth_layer_31to0[0] = 1'b1;
end
4'b0010:begin
fifth_layer_31to0[1] = 1'b1;
fifth_layer_31to0[0] = 1'b0;
end
4'b0100:begin
fifth_layer_31to0[1] = 1'b0;
fifth_layer_31to0[0] = 1'b1;
end
4'b0101:begin
fifth_layer_31to0[1] = 1'b1;
fifth_layer_31to0[0] = 1'b0;
end
4'b0110:begin
fifth_layer_31to0[1] = 1'b0;
fifth_layer_31to0[0] = 1'b0;
end
4'b1000:begin
fifth_layer_31to0[1] = 1'b1;
fifth_layer_31to0[0] = 1'b0;
end
4'b1001:begin
fifth_layer_31to0[1] = 1'b0;
fifth_layer_31to0[0] = 1'b0;
end
4'b1010:begin
fifth_layer_31to0[1] = 1'b0;
fifth_layer_31to0[0] = 1'b1;
end
default: begin // Needed to prevent latches from being inferred
fifth_layer_31to0[1] = 1'b0;
fifth_layer_31to0[0] = 1'b0;
end
endcase
end // always

always @ (forth_layer_63to48 or forth_layer_47to32)
begin

case ({forth_layer_63to48[1:0],forth_layer_47to32[1:0]})
4'b0000:begin
fifth_layer_63to32[1] = 1'b0;
fifth_layer_63to32[0] = 1'b0;
end
4'b0001:begin
fifth_layer_63to32[1] = 1'b0;
fifth_layer_63to32[0] = 1'b1;
end
4'b0010:begin
fifth_layer_63to32[1] = 1'b1;
fifth_layer_63to32[0] = 1'b0;
end
4'b0100:begin
fifth_layer_63to32[1] = 1'b0;
fifth_layer_63to32[0] = 1'b1;
end
4'b0101:begin
fifth_layer_63to32[1] = 1'b1;
fifth_layer_63to32[0] = 1'b0;
end
4'b0110:begin
fifth_layer_63to32[1] = 1'b0;
fifth_layer_63to32[0] = 1'b0;
end
4'b1000:begin
fifth_layer_63to32[1] = 1'b1;
fifth_layer_63to32[0] = 1'b0;
end
4'b1001:begin
fifth_layer_63to32[1] = 1'b0;
fifth_layer_63to32[0] = 1'b0;
end
4'b1010:begin
fifth_layer_63to32[1] = 1'b0;
fifth_layer_63to32[0] = 1'b1;
end
default: begin // Needed to prevent latches from being inferred
fifth_layer_63to32[1] = 1'b0;
fifth_layer_63to32[0] = 1'b0;
end
endcase
end // always



always @ (fifth_layer_63to32 or fifth_layer_31to0)
begin

case ({fifth_layer_63to32[1:0],fifth_layer_31to0[1:0]})
4'b0000:begin
result_mod3[1] = 1'b0;
result_mod3[0] = 1'b0;
end
4'b0001:begin
result_mod3[1] = 1'b0;
result_mod3[0] = 1'b1;
end
4'b0010:begin
result_mod3[1] = 1'b1;
result_mod3[0] = 1'b0;
end
4'b0100:begin
result_mod3[1] = 1'b0;
result_mod3[0] = 1'b1;
end
4'b0101:begin
result_mod3[1] = 1'b1;
result_mod3[0] = 1'b0;
end
4'b0110:begin
result_mod3[1] = 1'b0;
result_mod3[0] = 1'b0;
end
4'b1000:begin
result_mod3[1] = 1'b1;
result_mod3[0] = 1'b0;
end
4'b1001:begin
result_mod3[1] = 1'b0;
result_mod3[0] = 1'b0;
end
4'b1010:begin
result_mod3[1] = 1'b0;
result_mod3[0] = 1'b1;
end
default: begin // Needed to prevent latches from being inferred
result_mod3[1] = 1'b0;
result_mod3[0] = 1'b0;
end
endcase
end // always


// *****************************************************************
// End of compute the modulo3 of reg_to_solve
// *****************************************************************



endmodule // modulo3_Nbit

tb_modulo3.v

//--------------------------------------------------------------------------
// Module : tb_modulo3
// Full Module Name : tb_modulo3.v
// Current Version : 1.0
// Version Date : June 3, 2009
//
// Description : Testbench for all Modulo3 Calculation of Registers
// 3-bit to 64-bit
//
// Comments for the theory and operation of the parameterized module,
// modulo3_Nbit.v For clarity, a few flattened, unparameterized modules
// are also shown, for 12bit, 13bit, 14bit, 15bit, 16bit and 36bit.
// These modules are not commented.
//--------------------------------------------------------------------------

`timescale 1 ns / 10 ps

`define clk_period_div2 5

`define bitsize 7'd47 // !!!



module tb_modulo3;

//--------------------------------------------------------------------------
// Signals for the Instantiated Blocks
//--------------------------------------------------------------------------

// tb signals
reg clk;
reg reset_n;
reg reset_n_delay;

reg [(`bitsize-1):0] reg_Nbit_to_solve;
wire [1:0] result_Nbit_mod3;
wire [1:0] result_Nbit_mod3_calc;
reg quick_check_result_Nbit_mod3;

reg [35:0] reg_36bit_to_solve;
wire [1:0] result_36bit_mod3;
reg [1:0] result_36bit_mod3_delay;
reg quick_check_result_36bit_mod3;

reg [35:0] reg_36bit_to_solve_lfsr;
wire [1:0] result_36bit_mod3_lfsr;
wire [1:0] result_36bit_mod3_calc_lfsr;
reg quick_check_result_36bit_mod3_lfsr;

reg [15:0] reg_16bit_to_solve;
wire [1:0] result_16bit_mod3;
reg [1:0] result_16bit_mod3_delay;
reg quick_check_result_16bit_mod3;

reg [14:0] reg_15bit_to_solve;
wire [1:0] result_15bit_mod3;
reg [1:0] result_15bit_mod3_delay;
reg quick_check_result_15bit_mod3;

reg [13:0] reg_14bit_to_solve;
wire [1:0] result_14bit_mod3;
reg [1:0] result_14bit_mod3_delay;
reg quick_check_result_14bit_mod3;

reg [12:0] reg_13bit_to_solve;
wire [1:0] result_13bit_mod3;
reg [1:0] result_13bit_mod3_delay;
reg quick_check_result_13bit_mod3;

reg [11:0] reg_12bit_to_solve;
wire [1:0] result_12bit_mod3;
reg [1:0] result_12bit_mod3_delay;
reg quick_check_result_12bit_mod3;


//--------------------------------------------------------------------------
// Main test
//--------------------------------------------------------------------------

initial
begin
clk = 1'b0;
reset_n = 1'b0;
#1000;
reset_n = 1'b1;
#1000000000;
reset_n = 1'b0;
end // initial

// generate clock
always
begin
#`clk_period_div2;
clk = ~clk;
end // always

always @ (posedge clk or negedge reset_n)
begin
if (reset_n == 1'b0)
begin
reset_n_delay = 1'b0;
end
else
begin
reset_n_delay = reset_n;
end
end // always

// 64-BIT LFSR COUNTER
// *******************************************************************************
// It takes too long to test big registers using just an incremental counter. For
// example, with 100MHz clock, it takes 687.194sec to test a 36bit register. An
// LFSR would also have to run for 687.194sec (one missing code however) for 100%
// coverage, but as a practical matter, you can run it for just a few msec and at
// least it will shortly exercise all bits - good enough testing.

//For a table of LFSR taps, go to http://home1.gte.net/res0658s/electronics/LFSRtaps.html
// The taps for a 64-bit LFSR are 64, 63, 61 and 60.

// 64-bit LFSR, repeats every 2^64/100MHz = 5849.42 years
reg [63:0] LFSR;
wire LFSR_D;
wire LFSR_D1;
wire LFSR_D2;
//
always @ (posedge clk or negedge reset_n)
begin
if (reset_n == 1'b0)
begin
LFSR = 64'hAAAA_AAAA_AAAA_AAAA;
end
else
begin
LFSR <= {LFSR[62:0],LFSR_D};
end
end

assign LFSR_D1 = LFSR[63] ~^ LFSR[62]; // Table says 64, 63, 61, 60
assign LFSR_D2 = LFSR[60] ~^ LFSR_D1;
assign LFSR_D = LFSR[59] ~^ LFSR_D2;
// *******************************************************************************


// N-BIT, TESTED WITH LFSR COUNTER
// *******************************************************************************
always @ (posedge clk or negedge reset_n)
begin
if (reset_n == 1'b0)
begin
reg_Nbit_to_solve <= 1'h0; // (`bitsize)'h0 oddly doesn't work;
end
else
begin
reg_Nbit_to_solve <= LFSR[(`bitsize-1):0];
end
end //always

modulo3_Nbit i_modulo3_Nbit (
// inputs
.reg_to_solve (reg_Nbit_to_solve),
// outputs
.result_mod3 (result_Nbit_mod3)
);

assign result_Nbit_mod3_calc = reg_Nbit_to_solve%3; //Need to use the simulator's
// modulo-3, as the LFSR is random. With incremental counter we can just increment.

always @ (negedge clk or negedge reset_n_delay)
begin
if (reset_n_delay == 1'b0) // delay one extra clock from reset_n
begin
quick_check_result_Nbit_mod3 = 1'b0;
end
else
begin
if (result_Nbit_mod3_calc == result_Nbit_mod3)
begin
quick_check_result_Nbit_mod3 = 1'b0;
end
else
begin
quick_check_result_Nbit_mod3 = 1'b1;
end
end
end // always
// *******************************************************************************



// FLAT 36-BIT, TESTED WITH INCREMENTAL COUNTER
// *******************************************************************************
// sim for 687194 ms (2^36/100000ms)
always @ (posedge clk or negedge reset_n)
begin
if (reset_n == 1'b0)
begin
reg_36bit_to_solve = 36'h000000000;
end
else if (reg_36bit_to_solve != 36'hFFFFFFFFF)
begin
reg_36bit_to_solve = reg_36bit_to_solve + 36'h000000001;
end
end // always

modulo3_36bit_flat i_modulo3_36bit_flat (
// inputs
.reg_to_solve (reg_36bit_to_solve),
// outputs
.result_mod3 (result_36bit_mod3)
);

always @ (posedge clk or negedge reset_n)
begin
if (reset_n == 1'b0)
begin
result_36bit_mod3_delay = 2'b00;
end
else
begin
result_36bit_mod3_delay = result_36bit_mod3;
end
end // always

always @ (negedge clk or negedge reset_n_delay)
begin
if (reset_n_delay == 1'b0) // delay one extra clock from reset_n
begin
quick_check_result_36bit_mod3 = 1'b0;
end
else
begin
if ( (result_36bit_mod3_delay == 2'b00) && (result_36bit_mod3 == 2'b01)
|| ( (result_36bit_mod3_delay == 2'b01) && (result_36bit_mod3 == 2'b10) )
|| ( (result_36bit_mod3_delay == 2'b10) && (result_36bit_mod3 == 2'b00) ) )
begin
quick_check_result_36bit_mod3 = 1'b0;
end
else
begin
quick_check_result_36bit_mod3 = 1'b1;
end
end
end // always
// *******************************************************************************


// FLAT 36-BIT, TESTED WITH LFSR COUNTER
// *******************************************************************************
always @ (posedge clk or negedge reset_n)
begin
if (reset_n == 1'b0)
begin
reg_36bit_to_solve_lfsr <= 36'h0;
end
else
begin
reg_36bit_to_solve_lfsr <= LFSR[35:0];
end
end //always

modulo3_36bit_flat i_modulo3_36bit_flat_lfsr (
// inputs
.reg_to_solve (reg_36bit_to_solve_lfsr),
// outputs
.result_mod3 (result_36bit_mod3_lfsr)
);

assign result_36bit_mod3_calc_lfsr = reg_36bit_to_solve_lfsr%3; //Need to use the simulator's
// modulo-3, as the LFSR is random. With incremental counter we can just increment.

always @ (negedge clk or negedge reset_n_delay)
begin
if (reset_n_delay == 1'b0) // delay one extra clock from reset_n
begin
quick_check_result_36bit_mod3_lfsr = 1'b0;
end
else
begin
if (result_36bit_mod3_calc_lfsr == result_36bit_mod3_lfsr)
begin
quick_check_result_36bit_mod3_lfsr = 1'b0;
end
else
begin
quick_check_result_36bit_mod3_lfsr = 1'b1;
end
end
end // always
// *******************************************************************************


// FLAT 16-BIT, TESTED WITH INCREMENTAL COUNTER
// *******************************************************************************
// Sim for 0.65636ms
always @ (posedge clk or negedge reset_n)
begin
if (reset_n == 1'b0)
begin
reg_16bit_to_solve = 16'h0000;
end
else if (reg_16bit_to_solve != 16'hFFFF)
begin
reg_16bit_to_solve = reg_16bit_to_solve + 16'h0001;
end
end // always

modulo3_16bit_flat i_modulo3_16bit_flat (
// inputs
.reg_to_solve (reg_16bit_to_solve),
// outputs
.result_mod3 (result_16bit_mod3)
);

always @ (posedge clk or negedge reset_n)
begin
if (reset_n == 1'b0)
begin
result_16bit_mod3_delay = 2'b00;
end
else
begin
result_16bit_mod3_delay = result_16bit_mod3;
end
end // always

always @ (negedge clk or negedge reset_n_delay)
begin
if (reset_n_delay == 1'b0) // delay one extra clock from reset_n
begin
quick_check_result_16bit_mod3 = 1'b0;
end
else
begin
if ( (result_16bit_mod3_delay == 2'b00) && (result_16bit_mod3 == 2'b01)
|| ( (result_16bit_mod3_delay == 2'b01) && (result_16bit_mod3 == 2'b10) )
|| ( (result_16bit_mod3_delay == 2'b10) && (result_16bit_mod3 == 2'b00) ) )
begin
quick_check_result_16bit_mod3 = 1'b0;
end
else
begin
quick_check_result_16bit_mod3 = 1'b1;
end
end
end // always
// *******************************************************************************




// FLAT 15-BIT, TESTED WITH INCREMENTAL COUNTER
// *******************************************************************************
// Sim for 0.32866ms
always @ (posedge clk or negedge reset_n)
begin
if (reset_n == 1'b0)
begin
reg_15bit_to_solve = 15'h000;
end
else if (reg_15bit_to_solve != 15'h7FFF)
begin
reg_15bit_to_solve = reg_15bit_to_solve + 15'h001;
end
end // always

modulo3_15bit_flat i_modulo3_15bit_flat (
// inputs
.reg_to_solve (reg_15bit_to_solve),
// outputs
.result_mod3 (result_15bit_mod3)
);

always @ (posedge clk or negedge reset_n)
begin
if (reset_n == 1'b0)
begin
result_15bit_mod3_delay = 2'b00;
end
else
begin
result_15bit_mod3_delay = result_15bit_mod3;
end
end // always

always @ (negedge clk or negedge reset_n_delay)
begin
if (reset_n_delay == 1'b0) // delay one extra clock from reset_n
begin
quick_check_result_15bit_mod3 = 1'b0;
end
else
begin
if ( (result_15bit_mod3_delay == 2'b00) && (result_15bit_mod3 == 2'b01)
|| ( (result_15bit_mod3_delay == 2'b01) && (result_15bit_mod3 == 2'b10) )
|| ( (result_15bit_mod3_delay == 2'b10) && (result_15bit_mod3 == 2'b00) ) )
begin
quick_check_result_15bit_mod3 = 1'b0;
end
else
begin
quick_check_result_15bit_mod3 = 1'b1;
end
end
end // always
// *******************************************************************************




// FLAT 14-BIT, TESTED WITH INCREMENTAL COUNTER
// *******************************************************************************
// Sim for 0.16484ms
always @ (posedge clk or negedge reset_n)
begin
if (reset_n == 1'b0)
begin
reg_14bit_to_solve = 14'h000;
end
else if (reg_14bit_to_solve != 14'h3FFF)
begin
reg_14bit_to_solve = reg_14bit_to_solve + 14'h001;
end
end // always

modulo3_14bit_flat i_modulo3_14bit_flat (
// inputs
.reg_to_solve (reg_14bit_to_solve),
// outputs
.result_mod3 (result_14bit_mod3)
);

always @ (posedge clk or negedge reset_n)
begin
if (reset_n == 1'b0)
begin
result_14bit_mod3_delay = 2'b00;
end
else
begin
result_14bit_mod3_delay = result_14bit_mod3;
end
end // always

always @ (negedge clk or negedge reset_n_delay)
begin
if (reset_n_delay == 1'b0) // delay one extra clock from reset_n
begin
quick_check_result_14bit_mod3 = 1'b0;
end
else
begin
if ( (result_14bit_mod3_delay == 2'b00) && (result_14bit_mod3 == 2'b01)
|| ( (result_14bit_mod3_delay == 2'b01) && (result_14bit_mod3 == 2'b10) )
|| ( (result_14bit_mod3_delay == 2'b10) && (result_14bit_mod3 == 2'b00) ) )
begin
quick_check_result_14bit_mod3 = 1'b0;
end
else
begin
quick_check_result_14bit_mod3 = 1'b1;
end
end
end // always
// *******************************************************************************




// FLAT 13-BIT, TESTED WITH INCREMENTAL COUNTER
// *******************************************************************************
// Sim for 0.08292ms
always @ (posedge clk or negedge reset_n)
begin
if (reset_n == 1'b0)
begin
reg_13bit_to_solve = 13'h000;
end
else if (reg_13bit_to_solve != 13'h1FFF)
begin
reg_13bit_to_solve = reg_13bit_to_solve + 13'h001;
end
end // always

modulo3_13bit_flat i_modulo3_13bit_flat (
// inputs
.reg_to_solve (reg_13bit_to_solve),
// outputs
.result_mod3 (result_13bit_mod3)
);

always @ (posedge clk or negedge reset_n)
begin
if (reset_n == 1'b0)
begin
result_13bit_mod3_delay = 2'b00;
end
else
begin
result_13bit_mod3_delay = result_13bit_mod3;
end
end // always

always @ (negedge clk or negedge reset_n_delay)
begin
if (reset_n_delay == 1'b0) // delay one extra clock from reset_n
begin
quick_check_result_13bit_mod3 = 1'b0;
end
else
begin
if ( (result_13bit_mod3_delay == 2'b00) && (result_13bit_mod3 == 2'b01)
|| ( (result_13bit_mod3_delay == 2'b01) && (result_13bit_mod3 == 2'b10) )
|| ( (result_13bit_mod3_delay == 2'b10) && (result_13bit_mod3 == 2'b00) ) )
begin
quick_check_result_13bit_mod3 = 1'b0;
end
else
begin
quick_check_result_13bit_mod3 = 1'b1;
end
end
end // always
// *******************************************************************************




// FLAT 12-BIT, TESTED WITH INCREMENTAL COUNTER
// *******************************************************************************
// Sim for 0.04196ms
always @ (posedge clk or negedge reset_n)
begin
if (reset_n == 1'b0)
begin
reg_12bit_to_solve = 12'h000;
end
else if (reg_12bit_to_solve != 12'hFFF)
begin
reg_12bit_to_solve = reg_12bit_to_solve + 12'h001;
end
end // always

modulo3_12bit_flat i_modulo3_12bit_flat (
// inputs
.reg_to_solve (reg_12bit_to_solve),
// outputs
.result_mod3 (result_12bit_mod3)
);

always @ (posedge clk or negedge reset_n)
begin
if (reset_n == 1'b0)
begin
result_12bit_mod3_delay = 2'b00;
end
else
begin
result_12bit_mod3_delay = result_12bit_mod3;
end
end // always

always @ (negedge clk or negedge reset_n_delay)
begin
if (reset_n_delay == 1'b0) // delay one extra clock from reset_n
begin
quick_check_result_12bit_mod3 = 1'b0;
end
else
begin
if ( (result_12bit_mod3_delay == 2'b00) && (result_12bit_mod3 == 2'b01)
|| ( (result_12bit_mod3_delay == 2'b01) && (result_12bit_mod3 == 2'b10) )
|| ( (result_12bit_mod3_delay == 2'b10) && (result_12bit_mod3 == 2'b00) ) )
begin
quick_check_result_12bit_mod3 = 1'b0;
end
else
begin
quick_check_result_12bit_mod3 = 1'b1;
end
end
end // always
// *******************************************************************************

endmodule // tb_modulo3

modulo3_12bit_flat.v

//--------------------------------------------------------------------------
// Module : modulo3_12bit_flat
// Full Module Name : modulo3_12bit_flat.v
// Current Version : 1.0
// Version Date : June 3, 2009
//
// Description : Modulo3 Combinatorial Calculation of 12-bit Register
//
//
// No comments here, this is just a flattened, 12-bit modulo-3, so the user
// can see the code structure more clearly without the clutter.
//--------------------------------------------------------------------------


module modulo3_12bit_flat (
// inputs
reg_to_solve,

// outputs
result_mod3
);


//--------------------------------------------------------------------------
// Inputs / Outputs Description
//--------------------------------------------------------------------------

input [15:0] reg_to_solve;
output [1:0] result_mod3;

//--------------------------------------------------------------------------
// Signal Declaration
//--------------------------------------------------------------------------

wire [11:0] first_layer;
reg [1:0] second_layer_3to0;
reg [1:0] second_layer_7to4;
reg [1:0] second_layer_11to8;
reg [1:0] third_layer_7to0;
//reg [1:0] third_layer_15to8;
reg [1:0] result_mod3;

// *****************************************************************
// Compute the modulo3 of reg_to_solve using combinational logic only
// *****************************************************************

//First examine the reg_to_solve pairs so that:
// 00 -> 00
// 01 -> 01
// 10 -> 10
// 11 -> 00
assign first_layer[0] = (reg_to_solve[1] ^ reg_to_solve[0]) & reg_to_solve[0];
assign first_layer[1] = (reg_to_solve[1] ^ reg_to_solve[0]) & reg_to_solve[1];
assign first_layer[2] = (reg_to_solve[3] ^ reg_to_solve[2]) & reg_to_solve[2];
assign first_layer[3] = (reg_to_solve[3] ^ reg_to_solve[2]) & reg_to_solve[3];
assign first_layer[4] = (reg_to_solve[5] ^ reg_to_solve[4]) & reg_to_solve[4];
assign first_layer[5] = (reg_to_solve[5] ^ reg_to_solve[4]) & reg_to_solve[5];
assign first_layer[6] = (reg_to_solve[7] ^ reg_to_solve[6]) & reg_to_solve[6];
assign first_layer[7] = (reg_to_solve[7] ^ reg_to_solve[6]) & reg_to_solve[7];
assign first_layer[8] = (reg_to_solve[9] ^ reg_to_solve[8]) & reg_to_solve[8];
assign first_layer[9] = (reg_to_solve[9] ^ reg_to_solve[8]) & reg_to_solve[9];
assign first_layer[10] = (reg_to_solve[11] ^ reg_to_solve[10]) & reg_to_solve[10];
assign first_layer[11] = (reg_to_solve[11] ^ reg_to_solve[10]) & reg_to_solve[11];

always @ (first_layer)
begin
// nine choices:
// 0000 -> 00
// 0001 -> 01
// 0010 -> 10
// 0100 -> 01
// 0101 -> 10
// 0110 -> 00
// 1000 -> 10
// 1001 -> 00
// 1010 -> 01
case (first_layer[3:0])
4'b0000: begin
second_layer_3to0[1] = 1'b0;
second_layer_3to0[0] = 1'b0;
end
4'b0001: begin
second_layer_3to0[1] = 1'b0;
second_layer_3to0[0] = 1'b1;
end
4'b0010: begin
second_layer_3to0[1] = 1'b1;
second_layer_3to0[0] = 1'b0;
end
4'b0100: begin
second_layer_3to0[1] = 1'b0;
second_layer_3to0[0] = 1'b1;
end
4'b0101: begin
second_layer_3to0[1] = 1'b1;
second_layer_3to0[0] = 1'b0;
end
4'b0110: begin
second_layer_3to0[1] = 1'b0;
second_layer_3to0[0] = 1'b0;
end
4'b1000: begin
second_layer_3to0[1] = 1'b1;
second_layer_3to0[0] = 1'b0;
end
4'b1001: begin
second_layer_3to0[1] = 1'b0;
second_layer_3to0[0] = 1'b0;
end
4'b1010: begin
second_layer_3to0[1] = 1'b0;
second_layer_3to0[0] = 1'b1;
end
default: begin // Needed to prevent latches being inferred
second_layer_3to0[1] = 1'b0;
second_layer_3to0[0] = 1'b0;
end
endcase

case (first_layer[7:4])
4'b0000:begin
second_layer_7to4[1] = 1'b0;
second_layer_7to4[0] = 1'b0;
end
4'b0001:begin
second_layer_7to4[1] = 1'b0;
second_layer_7to4[0] = 1'b1;
end
4'b0010:begin
second_layer_7to4[1] = 1'b1;
second_layer_7to4[0] = 1'b0;
end
4'b0100:begin
second_layer_7to4[1] = 1'b0;
second_layer_7to4[0] = 1'b1;
end
4'b0101:begin
second_layer_7to4[1] = 1'b1;
second_layer_7to4[0] = 1'b0;
end
4'b0110:begin
second_layer_7to4[1] = 1'b0;
second_layer_7to4[0] = 1'b0;
end
4'b1000:begin
second_layer_7to4[1] = 1'b1;
second_layer_7to4[0] = 1'b0;
end
4'b1001:begin
second_layer_7to4[1] = 1'b0;
second_layer_7to4[0] = 1'b0;
end
4'b1010:begin
second_layer_7to4[1] = 1'b0;
second_layer_7to4[0] = 1'b1;
end
default: begin // Needed to prevent latches being inferred
second_layer_7to4[1] = 1'b0;
second_layer_7to4[0] = 1'b0;
end
endcase


case (first_layer[11:8])
4'b0000:begin
second_layer_11to8[1] = 1'b0;
second_layer_11to8[0] = 1'b0;
end
4'b0001:begin
second_layer_11to8[1] = 1'b0;
second_layer_11to8[0] = 1'b1;
end
4'b0010:begin
second_layer_11to8[1] = 1'b1;
second_layer_11to8[0] = 1'b0;
end
4'b0100:begin
second_layer_11to8[1] = 1'b0;
second_layer_11to8[0] = 1'b1;
end
4'b0101:begin
second_layer_11to8[1] = 1'b1;
second_layer_11to8[0] = 1'b0;
end
4'b0110:begin
second_layer_11to8[1] = 1'b0;
second_layer_11to8[0] = 1'b0;
end
4'b1000:begin
second_layer_11to8[1] = 1'b1;
second_layer_11to8[0] = 1'b0;
end
4'b1001:begin
second_layer_11to8[1] = 1'b0;
second_layer_11to8[0] = 1'b0;
end
4'b1010:begin
second_layer_11to8[1] = 1'b0;
second_layer_11to8[0] = 1'b1;
end
default: begin // Needed to prevent latches being inferred
second_layer_11to8[1] = 1'b0;
second_layer_11to8[0] = 1'b0;
end
endcase
end //always


always @ (second_layer_7to4 or second_layer_3to0)
begin
case ({second_layer_7to4[1:0],second_layer_3to0[1:0]})
4'b0000:begin
third_layer_7to0[1] = 1'b0;
third_layer_7to0[0] = 1'b0;
end
4'b0001:begin
third_layer_7to0[1] = 1'b0;
third_layer_7to0[0] = 1'b1;
end
4'b0010:begin
third_layer_7to0[1] = 1'b1;
third_layer_7to0[0] = 1'b0;
end
4'b0100:begin
third_layer_7to0[1] = 1'b0;
third_layer_7to0[0] = 1'b1;
end
4'b0101:begin
third_layer_7to0[1] = 1'b1;
third_layer_7to0[0] = 1'b0;
end
4'b0110:begin
third_layer_7to0[1] = 1'b0;
third_layer_7to0[0] = 1'b0;
end
4'b1000:begin
third_layer_7to0[1] = 1'b1;
third_layer_7to0[0] = 1'b0;
end
4'b1001:begin
third_layer_7to0[1] = 1'b0;
third_layer_7to0[0] = 1'b0;
end
4'b1010:begin
third_layer_7to0[1] = 1'b0;
third_layer_7to0[0] = 1'b1;
end
default: begin // Needed to prevent latches being inferred
third_layer_7to0[1] = 1'b0;
third_layer_7to0[0] = 1'b0;
end
endcase
end // always

always @ (second_layer_11to8 or third_layer_7to0)
begin
// for 12-bit use second_layer_11to8 rather than creating third_layer_15to8
// However there is an offset of 2
// So what was 00 --> 01
// What was 01 --> 10
// What was 10 --> 00

case ({second_layer_11to8[1:0],third_layer_7to0[1:0]})
4'b0000:begin
result_mod3[1] = 1'b0;
result_mod3[0] = 1'b0;
end
4'b0001:begin
result_mod3[1] = 1'b0;
result_mod3[0] = 1'b1;
end
4'b0010:begin
result_mod3[1] = 1'b1;
result_mod3[0] = 1'b0;
end
4'b0100:begin
result_mod3[1] = 1'b0;
result_mod3[0] = 1'b1;
end
4'b0101:begin
result_mod3[1] = 1'b1;
result_mod3[0] = 1'b0;
end
4'b0110:begin
result_mod3[1] = 1'b0;
result_mod3[0] = 1'b0;
end
4'b1000:begin
result_mod3[1] = 1'b1;
result_mod3[0] = 1'b0;
end
4'b1001:begin
result_mod3[1] = 1'b0;
result_mod3[0] = 1'b0;
end
4'b1010:begin
result_mod3[1] = 1'b0;
result_mod3[0] = 1'b1;
end
default: begin // Needed to prevent latches being inferred
result_mod3[1] = 1'b0;
result_mod3[0] = 1'b0;
end
endcase
end // always

// *****************************************************************
// End of compute the modulo3 of reg_to_solve
// *****************************************************************



endmodule // modulo3_12bit_flat

modulo3_13bit_flat.v

//--------------------------------------------------------------------------
// Module : modulo3_13bit_flat
// Full Module Name : modulo3_13bit_flat.v
// Current Version : 1.0
// Version Date : June 8, 2009
//
// Description : Modulo3 Combinatorial Calculation of 13-bit Register
//
//
// No comments here, this is just a flattened, 13-bit modulo-3, so the user
// can see the code structure more clearly without the clutter.
//--------------------------------------------------------------------------


module modulo3_13bit_flat (
// inputs
reg_to_solve,

// outputs
result_mod3
);


//--------------------------------------------------------------------------
// Inputs / Outputs Description
//--------------------------------------------------------------------------

input [12:0] reg_to_solve;
output [1:0] result_mod3;

//--------------------------------------------------------------------------
// Signal Declaration
//--------------------------------------------------------------------------

wire [12:0] first_layer;
reg [1:0] second_layer_3to0;
reg [1:0] second_layer_7to4;
reg [1:0] second_layer_11to8;
reg [1:0] third_layer_7to0;
reg [1:0] third_layer_12to8;
reg [1:0] result_mod3;

// *****************************************************************
// Compute the modulo3 of reg_to_solve using combinational logic only
// *****************************************************************

//First examine the reg_to_solve pairs so that:
// 00 -> 00
// 01 -> 01
// 10 -> 10
// 11 -> 00
assign first_layer[0] = (reg_to_solve[1] ^ reg_to_solve[0]) & reg_to_solve[0];
assign first_layer[1] = (reg_to_solve[1] ^ reg_to_solve[0]) & reg_to_solve[1];
assign first_layer[2] = (reg_to_solve[3] ^ reg_to_solve[2]) & reg_to_solve[2];
assign first_layer[3] = (reg_to_solve[3] ^ reg_to_solve[2]) & reg_to_solve[3];
assign first_layer[4] = (reg_to_solve[5] ^ reg_to_solve[4]) & reg_to_solve[4];
assign first_layer[5] = (reg_to_solve[5] ^ reg_to_solve[4]) & reg_to_solve[5];
assign first_layer[6] = (reg_to_solve[7] ^ reg_to_solve[6]) & reg_to_solve[6];
assign first_layer[7] = (reg_to_solve[7] ^ reg_to_solve[6]) & reg_to_solve[7];
assign first_layer[8] = (reg_to_solve[9] ^ reg_to_solve[8]) & reg_to_solve[8];
assign first_layer[9] = (reg_to_solve[9] ^ reg_to_solve[8]) & reg_to_solve[9];
assign first_layer[10] = (reg_to_solve[11] ^ reg_to_solve[10]) & reg_to_solve[10];
assign first_layer[11] = (reg_to_solve[11] ^ reg_to_solve[10]) & reg_to_solve[11];
assign first_layer[12] = reg_to_solve[12];

always @ (first_layer)
begin
// nine choices:
// 0000 -> 00
// 0001 -> 01
// 0010 -> 10
// 0100 -> 01
// 0101 -> 10
// 0110 -> 00
// 1000 -> 10
// 1001 -> 00
// 1010 -> 01
case (first_layer[3:0])
4'b0000: begin
second_layer_3to0[1] = 1'b0;
second_layer_3to0[0] = 1'b0;
end
4'b0001: begin
second_layer_3to0[1] = 1'b0;
second_layer_3to0[0] = 1'b1;
end
4'b0010: begin
second_layer_3to0[1] = 1'b1;
second_layer_3to0[0] = 1'b0;
end
4'b0100: begin
second_layer_3to0[1] = 1'b0;
second_layer_3to0[0] = 1'b1;
end
4'b0101: begin
second_layer_3to0[1] = 1'b1;
second_layer_3to0[0] = 1'b0;
end
4'b0110: begin
second_layer_3to0[1] = 1'b0;
second_layer_3to0[0] = 1'b0;
end
4'b1000: begin
second_layer_3to0[1] = 1'b1;
second_layer_3to0[0] = 1'b0;
end
4'b1001: begin
second_layer_3to0[1] = 1'b0;
second_layer_3to0[0] = 1'b0;
end
4'b1010: begin
second_layer_3to0[1] = 1'b0;
second_layer_3to0[0] = 1'b1;
end
default: begin // Needed to prevent latches being inferred
second_layer_3to0[1] = 1'b0;
second_layer_3to0[0] = 1'b0;
end
endcase

case (first_layer[7:4])
4'b0000:begin
second_layer_7to4[1] = 1'b0;
second_layer_7to4[0] = 1'b0;
end
4'b0001:begin
second_layer_7to4[1] = 1'b0;
second_layer_7to4[0] = 1'b1;
end
4'b0010:begin
second_layer_7to4[1] = 1'b1;
second_layer_7to4[0] = 1'b0;
end
4'b0100:begin
second_layer_7to4[1] = 1'b0;
second_layer_7to4[0] = 1'b1;
end
4'b0101:begin
second_layer_7to4[1] = 1'b1;
second_layer_7to4[0] = 1'b0;
end
4'b0110:begin
second_layer_7to4[1] = 1'b0;
second_layer_7to4[0] = 1'b0;
end
4'b1000:begin
second_layer_7to4[1] = 1'b1;
second_layer_7to4[0] = 1'b0;
end
4'b1001:begin
second_layer_7to4[1] = 1'b0;
second_layer_7to4[0] = 1'b0;
end
4'b1010:begin
second_layer_7to4[1] = 1'b0;
second_layer_7to4[0] = 1'b1;
end
default: begin // Needed to prevent latches being inferred
second_layer_7to4[1] = 1'b0;
second_layer_7to4[0] = 1'b0;
end
endcase


case (first_layer[11:8])
4'b0000:begin
second_layer_11to8[1] = 1'b0;
second_layer_11to8[0] = 1'b0;
end
4'b0001:begin
second_layer_11to8[1] = 1'b0;
second_layer_11to8[0] = 1'b1;
end
4'b0010:begin
second_layer_11to8[1] = 1'b1;
second_layer_11to8[0] = 1'b0;
end
4'b0100:begin
second_layer_11to8[1] = 1'b0;
second_layer_11to8[0] = 1'b1;
end
4'b0101:begin
second_layer_11to8[1] = 1'b1;
second_layer_11to8[0] = 1'b0;
end
4'b0110:begin
second_layer_11to8[1] = 1'b0;
second_layer_11to8[0] = 1'b0;
end
4'b1000:begin
second_layer_11to8[1] = 1'b1;
second_layer_11to8[0] = 1'b0;
end
4'b1001:begin
second_layer_11to8[1] = 1'b0;
second_layer_11to8[0] = 1'b0;
end
4'b1010:begin
second_layer_11to8[1] = 1'b0;
second_layer_11to8[0] = 1'b1;
end
default: begin // Needed to prevent latches being inferred
second_layer_11to8[1] = 1'b0;
second_layer_11to8[0] = 1'b0;
end
endcase


end //always


always @ (second_layer_7to4 or second_layer_3to0)
begin
case ({second_layer_7to4[1:0],second_layer_3to0[1:0]})
4'b0000:begin
third_layer_7to0[1] = 1'b0;
third_layer_7to0[0] = 1'b0;
end
4'b0001:begin
third_layer_7to0[1] = 1'b0;
third_layer_7to0[0] = 1'b1;
end
4'b0010:begin
third_layer_7to0[1] = 1'b1;
third_layer_7to0[0] = 1'b0;
end
4'b0100:begin
third_layer_7to0[1] = 1'b0;
third_layer_7to0[0] = 1'b1;
end
4'b0101:begin
third_layer_7to0[1] = 1'b1;
third_layer_7to0[0] = 1'b0;
end
4'b0110:begin
third_layer_7to0[1] = 1'b0;
third_layer_7to0[0] = 1'b0;
end
4'b1000:begin
third_layer_7to0[1] = 1'b1;
third_layer_7to0[0] = 1'b0;
end
4'b1001:begin
third_layer_7to0[1] = 1'b0;
third_layer_7to0[0] = 1'b0;
end
4'b1010:begin
third_layer_7to0[1] = 1'b0;
third_layer_7to0[0] = 1'b1;
end
default: begin // Needed to prevent latches being inferred
third_layer_7to0[1] = 1'b0;
third_layer_7to0[0] = 1'b0;
end
endcase
end // always

always @ (first_layer or second_layer_11to8)
begin

case ({first_layer[12],second_layer_11to8[1:0]})
3'b000:begin
third_layer_12to8[1] = 1'b0;
third_layer_12to8[0] = 1'b0;
end
3'b001:begin
third_layer_12to8[1] = 1'b0;
third_layer_12to8[0] = 1'b1;
end
3'b010:begin
third_layer_12to8[1] = 1'b1;
third_layer_12to8[0] = 1'b0;
end
3'b100:begin
third_layer_12to8[1] = 1'b0;
third_layer_12to8[0] = 1'b1;
end
3'b101:begin
third_layer_12to8[1] = 1'b1;
third_layer_12to8[0] = 1'b0;
end
3'b110:begin
third_layer_12to8[1] = 1'b0;
third_layer_12to8[0] = 1'b0;
end
default: begin // Needed to prevent latches being inferred
third_layer_12to8[1] = 1'b0;
third_layer_12to8[0] = 1'b0;
end
endcase
end // always


always @ (third_layer_12to8 or third_layer_7to0)
begin

case ({third_layer_12to8[1:0],third_layer_7to0[1:0]})
4'b0000:begin
result_mod3[1] = 1'b0;
result_mod3[0] = 1'b0;
end
4'b0001:begin
result_mod3[1] = 1'b0;
result_mod3[0] = 1'b1;
end
4'b0010:begin
result_mod3[1] = 1'b1;
result_mod3[0] = 1'b0;
end
4'b0100:begin
result_mod3[1] = 1'b0;
result_mod3[0] = 1'b1;
end
4'b0101:begin
result_mod3[1] = 1'b1;
result_mod3[0] = 1'b0;
end
4'b0110:begin
result_mod3[1] = 1'b0;
result_mod3[0] = 1'b0;
end
4'b1000:begin
result_mod3[1] = 1'b1;
result_mod3[0] = 1'b0;
end
4'b1001:begin
result_mod3[1] = 1'b0;
result_mod3[0] = 1'b0;
end
4'b1010:begin
result_mod3[1] = 1'b0;
result_mod3[0] = 1'b1;
end
default: begin // Needed to prevent latches being inferred
result_mod3[1] = 1'b0;
result_mod3[0] = 1'b0;
end
endcase
end // always


// *****************************************************************
// End of compute the modulo3 of reg_to_solve
// *****************************************************************



endmodule // modulo3_13bit_flat

modulo3_14bit_flat.v

//--------------------------------------------------------------------------
// Module : modulo3_14bit_flat
// Full Module Name : modulo3_14bit_flat.v
// Current Version : 1.0
// Version Date : June 8, 2009
//
// Description : Modulo3 Combinatorial Calculation of 14-bit Register
//
//
// No comments here, this is just a flattened, 14-bit modulo-3, so the user
// can see the code structure more clearly without the clutter.
//--------------------------------------------------------------------------


module modulo3_14bit_flat (
// inputs
reg_to_solve,

// outputs
result_mod3
);


//--------------------------------------------------------------------------
// Inputs / Outputs Description
//--------------------------------------------------------------------------

input [13:0] reg_to_solve;
output [1:0] result_mod3;

//--------------------------------------------------------------------------
// Signal Declaration
//--------------------------------------------------------------------------

wire [13:0] first_layer;
reg [1:0] second_layer_3to0;
reg [1:0] second_layer_7to4;
reg [1:0] second_layer_11to8;
reg [1:0] third_layer_7to0;
reg [1:0] third_layer_13to8;
reg [1:0] result_mod3;

// *****************************************************************
// Compute the modulo3 of reg_to_solve using combinational logic only
// *****************************************************************

//First examine the reg_to_solve pairs so that:
// 00 -> 00
// 01 -> 01
// 10 -> 10
// 11 -> 00
assign first_layer[0] = (reg_to_solve[1] ^ reg_to_solve[0]) & reg_to_solve[0];
assign first_layer[1] = (reg_to_solve[1] ^ reg_to_solve[0]) & reg_to_solve[1];
assign first_layer[2] = (reg_to_solve[3] ^ reg_to_solve[2]) & reg_to_solve[2];
assign first_layer[3] = (reg_to_solve[3] ^ reg_to_solve[2]) & reg_to_solve[3];
assign first_layer[4] = (reg_to_solve[5] ^ reg_to_solve[4]) & reg_to_solve[4];
assign first_layer[5] = (reg_to_solve[5] ^ reg_to_solve[4]) & reg_to_solve[5];
assign first_layer[6] = (reg_to_solve[7] ^ reg_to_solve[6]) & reg_to_solve[6];
assign first_layer[7] = (reg_to_solve[7] ^ reg_to_solve[6]) & reg_to_solve[7];
assign first_layer[8] = (reg_to_solve[9] ^ reg_to_solve[8]) & reg_to_solve[8];
assign first_layer[9] = (reg_to_solve[9] ^ reg_to_solve[8]) & reg_to_solve[9];
assign first_layer[10] = (reg_to_solve[11] ^ reg_to_solve[10]) & reg_to_solve[10];
assign first_layer[11] = (reg_to_solve[11] ^ reg_to_solve[10]) & reg_to_solve[11];
assign first_layer[12] = (reg_to_solve[13] ^ reg_to_solve[12]) & reg_to_solve[12];
assign first_layer[13] = (reg_to_solve[13] ^ reg_to_solve[12]) & reg_to_solve[13];

always @ (first_layer)
begin
// nine choices:
// 0000 -> 00
// 0001 -> 01
// 0010 -> 10
// 0100 -> 01
// 0101 -> 10
// 0110 -> 00
// 1000 -> 10
// 1001 -> 00
// 1010 -> 01
case (first_layer[3:0])
4'b0000: begin
second_layer_3to0[1] = 1'b0;
second_layer_3to0[0] = 1'b0;
end
4'b0001: begin
second_layer_3to0[1] = 1'b0;
second_layer_3to0[0] = 1'b1;
end
4'b0010: begin
second_layer_3to0[1] = 1'b1;
second_layer_3to0[0] = 1'b0;
end
4'b0100: begin
second_layer_3to0[1] = 1'b0;
second_layer_3to0[0] = 1'b1;
end
4'b0101: begin
second_layer_3to0[1] = 1'b1;
second_layer_3to0[0] = 1'b0;
end
4'b0110: begin
second_layer_3to0[1] = 1'b0;
second_layer_3to0[0] = 1'b0;
end
4'b1000: begin
second_layer_3to0[1] = 1'b1;
second_layer_3to0[0] = 1'b0;
end
4'b1001: begin
second_layer_3to0[1] = 1'b0;
second_layer_3to0[0] = 1'b0;
end
4'b1010: begin
second_layer_3to0[1] = 1'b0;
second_layer_3to0[0] = 1'b1;
end
default: begin // Needed to prevent latches being inferred
second_layer_3to0[1] = 1'b0;
second_layer_3to0[0] = 1'b0;
end
endcase

case (first_layer[7:4])
4'b0000:begin
second_layer_7to4[1] = 1'b0;
second_layer_7to4[0] = 1'b0;
end
4'b0001:begin
second_layer_7to4[1] = 1'b0;
second_layer_7to4[0] = 1'b1;
end
4'b0010:begin
second_layer_7to4[1] = 1'b1;
second_layer_7to4[0] = 1'b0;
end
4'b0100:begin
second_layer_7to4[1] = 1'b0;
second_layer_7to4[0] = 1'b1;
end
4'b0101:begin
second_layer_7to4[1] = 1'b1;
second_layer_7to4[0] = 1'b0;
end
4'b0110:begin
second_layer_7to4[1] = 1'b0;
second_layer_7to4[0] = 1'b0;
end
4'b1000:begin
second_layer_7to4[1] = 1'b1;
second_layer_7to4[0] = 1'b0;
end
4'b1001:begin
second_layer_7to4[1] = 1'b0;
second_layer_7to4[0] = 1'b0;
end
4'b1010:begin
second_layer_7to4[1] = 1'b0;
second_layer_7to4[0] = 1'b1;
end
default: begin // Needed to prevent latches being inferred
second_layer_7to4[1] = 1'b0;
second_layer_7to4[0] = 1'b0;
end
endcase


case (first_layer[11:8])
4'b0000:begin
second_layer_11to8[1] = 1'b0;
second_layer_11to8[0] = 1'b0;
end
4'b0001:begin
second_layer_11to8[1] = 1'b0;
second_layer_11to8[0] = 1'b1;
end
4'b0010:begin
second_layer_11to8[1] = 1'b1;
second_layer_11to8[0] = 1'b0;
end
4'b0100:begin
second_layer_11to8[1] = 1'b0;
second_layer_11to8[0] = 1'b1;
end
4'b0101:begin
second_layer_11to8[1] = 1'b1;
second_layer_11to8[0] = 1'b0;
end
4'b0110:begin
second_layer_11to8[1] = 1'b0;
second_layer_11to8[0] = 1'b0;
end
4'b1000:begin
second_layer_11to8[1] = 1'b1;
second_layer_11to8[0] = 1'b0;
end
4'b1001:begin
second_layer_11to8[1] = 1'b0;
second_layer_11to8[0] = 1'b0;
end
4'b1010:begin
second_layer_11to8[1] = 1'b0;
second_layer_11to8[0] = 1'b1;
end
default: begin // Needed to prevent latches being inferred
second_layer_11to8[1] = 1'b0;
second_layer_11to8[0] = 1'b0;
end
endcase


end //always


always @ (second_layer_7to4 or second_layer_3to0)
begin
case ({second_layer_7to4[1:0],second_layer_3to0[1:0]})
4'b0000:begin
third_layer_7to0[1] = 1'b0;
third_layer_7to0[0] = 1'b0;
end
4'b0001:begin
third_layer_7to0[1] = 1'b0;
third_layer_7to0[0] = 1'b1;
end
4'b0010:begin
third_layer_7to0[1] = 1'b1;
third_layer_7to0[0] = 1'b0;
end
4'b0100:begin
third_layer_7to0[1] = 1'b0;
third_layer_7to0[0] = 1'b1;
end
4'b0101:begin
third_layer_7to0[1] = 1'b1;
third_layer_7to0[0] = 1'b0;
end
4'b0110:begin
third_layer_7to0[1] = 1'b0;
third_layer_7to0[0] = 1'b0;
end
4'b1000:begin
third_layer_7to0[1] = 1'b1;
third_layer_7to0[0] = 1'b0;
end
4'b1001:begin
third_layer_7to0[1] = 1'b0;
third_layer_7to0[0] = 1'b0;
end
4'b1010:begin
third_layer_7to0[1] = 1'b0;
third_layer_7to0[0] = 1'b1;
end
default: begin // Needed to prevent latches being inferred
third_layer_7to0[1] = 1'b0;
third_layer_7to0[0] = 1'b0;
end
endcase
end // always

always @ (first_layer or second_layer_11to8)
begin

case ({first_layer[13], first_layer[12], second_layer_11to8[1:0]})
4'b0000:begin
third_layer_13to8[1] = 1'b0;
third_layer_13to8[0] = 1'b0;
end
4'b0001:begin
third_layer_13to8[1] = 1'b0;
third_layer_13to8[0] = 1'b1;
end
4'b0010:begin
third_layer_13to8[1] = 1'b1;
third_layer_13to8[0] = 1'b0;
end
4'b0100:begin
third_layer_13to8[1] = 1'b0;
third_layer_13to8[0] = 1'b1;
end
4'b0101:begin
third_layer_13to8[1] = 1'b1;
third_layer_13to8[0] = 1'b0;
end
4'b0110:begin
third_layer_13to8[1] = 1'b0;
third_layer_13to8[0] = 1'b0;
end
4'b1000:begin
third_layer_13to8[1] = 1'b1;
third_layer_13to8[0] = 1'b0;
end
4'b1001:begin
third_layer_13to8[1] = 1'b0;
third_layer_13to8[0] = 1'b0;
end
4'b1010:begin
third_layer_13to8[1] = 1'b0;
third_layer_13to8[0] = 1'b1;
end
default: begin // Needed to prevent latches being inferred
third_layer_13to8[1] = 1'b0;
third_layer_13to8[0] = 1'b0;
end
endcase
end // always


always @ (third_layer_13to8 or third_layer_7to0)
begin

case ({third_layer_13to8[1:0],third_layer_7to0[1:0]})
4'b0000:begin
result_mod3[1] = 1'b0;
result_mod3[0] = 1'b0;
end
4'b0001:begin
result_mod3[1] = 1'b0;
result_mod3[0] = 1'b1;
end
4'b0010:begin
result_mod3[1] = 1'b1;
result_mod3[0] = 1'b0;
end
4'b0100:begin
result_mod3[1] = 1'b0;
result_mod3[0] = 1'b1;
end
4'b0101:begin
result_mod3[1] = 1'b1;
result_mod3[0] = 1'b0;
end
4'b0110:begin
result_mod3[1] = 1'b0;
result_mod3[0] = 1'b0;
end
4'b1000:begin
result_mod3[1] = 1'b1;
result_mod3[0] = 1'b0;
end
4'b1001:begin
result_mod3[1] = 1'b0;
result_mod3[0] = 1'b0;
end
4'b1010:begin
result_mod3[1] = 1'b0;
result_mod3[0] = 1'b1;
end
default: begin // Needed to prevent latches being inferred
result_mod3[1] = 1'b0;
result_mod3[0] = 1'b0;
end
endcase
end // always


// *****************************************************************
// End of compute the modulo3 of reg_to_solve
// *****************************************************************



endmodule // modulo3_14bit_flat

modulo3_15bit_flat.v

//--------------------------------------------------------------------------
// Module : modulo3_15bit_flat
// Full Module Name : modulo3_15bit_flat.v
// Current Version : 1.0
// Version Date : June 8, 2009
//
// Description : Modulo3 Combinatorial Calculation of 15-bit Register
//
//
// No comments here, this is just a flattened, 15-bit modulo-3, so the user
// can see the code structure more clearly without the clutter.
//--------------------------------------------------------------------------

module modulo3_15bit_flat (
// inputs
reg_to_solve,

// outputs
result_mod3
);


//--------------------------------------------------------------------------
// Inputs / Outputs Description
//--------------------------------------------------------------------------

input [14:0] reg_to_solve;
output [1:0] result_mod3;

//--------------------------------------------------------------------------
// Signal Declaration
//--------------------------------------------------------------------------

wire [14:0] first_layer;
reg [1:0] second_layer_3to0;
reg [1:0] second_layer_7to4;
reg [1:0] second_layer_11to8;
reg [1:0] second_layer_14to12;
reg [1:0] third_layer_7to0;
reg [1:0] third_layer_14to8;
reg [1:0] result_mod3;

// *****************************************************************
// Compute the modulo3 of reg_to_solve using combinational logic only
// *****************************************************************

//First examine the reg_to_solve pairs so that:
// 00 -> 00
// 01 -> 01
// 10 -> 10
// 11 -> 00
assign first_layer[0] = (reg_to_solve[1] ^ reg_to_solve[0]) & reg_to_solve[0];
assign first_layer[1] = (reg_to_solve[1] ^ reg_to_solve[0]) & reg_to_solve[1];
assign first_layer[2] = (reg_to_solve[3] ^ reg_to_solve[2]) & reg_to_solve[2];
assign first_layer[3] = (reg_to_solve[3] ^ reg_to_solve[2]) & reg_to_solve[3];
assign first_layer[4] = (reg_to_solve[5] ^ reg_to_solve[4]) & reg_to_solve[4];
assign first_layer[5] = (reg_to_solve[5] ^ reg_to_solve[4]) & reg_to_solve[5];
assign first_layer[6] = (reg_to_solve[7] ^ reg_to_solve[6]) & reg_to_solve[6];
assign first_layer[7] = (reg_to_solve[7] ^ reg_to_solve[6]) & reg_to_solve[7];
assign first_layer[8] = (reg_to_solve[9] ^ reg_to_solve[8]) & reg_to_solve[8];
assign first_layer[9] = (reg_to_solve[9] ^ reg_to_solve[8]) & reg_to_solve[9];
assign first_layer[10] = (reg_to_solve[11] ^ reg_to_solve[10]) & reg_to_solve[10];
assign first_layer[11] = (reg_to_solve[11] ^ reg_to_solve[10]) & reg_to_solve[11];
assign first_layer[12] = (reg_to_solve[13] ^ reg_to_solve[12]) & reg_to_solve[12];
assign first_layer[13] = (reg_to_solve[13] ^ reg_to_solve[12]) & reg_to_solve[13];
assign first_layer[14] = reg_to_solve[14];

always @ (first_layer)
begin
// nine choices:
// 0000 -> 00
// 0001 -> 01
// 0010 -> 10
// 0100 -> 01
// 0101 -> 10
// 0110 -> 00
// 1000 -> 10
// 1001 -> 00
// 1010 -> 01
case (first_layer[3:0])
4'b0000: begin
second_layer_3to0[1] = 1'b0;
second_layer_3to0[0] = 1'b0;
end
4'b0001: begin
second_layer_3to0[1] = 1'b0;
second_layer_3to0[0] = 1'b1;
end
4'b0010: begin
second_layer_3to0[1] = 1'b1;
second_layer_3to0[0] = 1'b0;
end
4'b0100: begin
second_layer_3to0[1] = 1'b0;
second_layer_3to0[0] = 1'b1;
end
4'b0101: begin
second_layer_3to0[1] = 1'b1;
second_layer_3to0[0] = 1'b0;
end
4'b0110: begin
second_layer_3to0[1] = 1'b0;
second_layer_3to0[0] = 1'b0;
end
4'b1000: begin
second_layer_3to0[1] = 1'b1;
second_layer_3to0[0] = 1'b0;
end
4'b1001: begin
second_layer_3to0[1] = 1'b0;
second_layer_3to0[0] = 1'b0;
end
4'b1010: begin
second_layer_3to0[1] = 1'b0;
second_layer_3to0[0] = 1'b1;
end
default: begin // Needed to prevent latches being inferred
second_layer_3to0[1] = 1'b0;
second_layer_3to0[0] = 1'b0;
end
endcase

case (first_layer[7:4])
4'b0000:begin
second_layer_7to4[1] = 1'b0;
second_layer_7to4[0] = 1'b0;
end
4'b0001:begin
second_layer_7to4[1] = 1'b0;
second_layer_7to4[0] = 1'b1;
end
4'b0010:begin
second_layer_7to4[1] = 1'b1;
second_layer_7to4[0] = 1'b0;
end
4'b0100:begin
second_layer_7to4[1] = 1'b0;
second_layer_7to4[0] = 1'b1;
end
4'b0101:begin
second_layer_7to4[1] = 1'b1;
second_layer_7to4[0] = 1'b0;
end
4'b0110:begin
second_layer_7to4[1] = 1'b0;
second_layer_7to4[0] = 1'b0;
end
4'b1000:begin
second_layer_7to4[1] = 1'b1;
second_layer_7to4[0] = 1'b0;
end
4'b1001:begin
second_layer_7to4[1] = 1'b0;
second_layer_7to4[0] = 1'b0;
end
4'b1010:begin
second_layer_7to4[1] = 1'b0;
second_layer_7to4[0] = 1'b1;
end
default: begin // Needed to prevent latches being inferred
second_layer_7to4[1] = 1'b0;
second_layer_7to4[0] = 1'b0;
end
endcase


case (first_layer[11:8])
4'b0000:begin
second_layer_11to8[1] = 1'b0;
second_layer_11to8[0] = 1'b0;
end
4'b0001:begin
second_layer_11to8[1] = 1'b0;
second_layer_11to8[0] = 1'b1;
end
4'b0010:begin
second_layer_11to8[1] = 1'b1;
second_layer_11to8[0] = 1'b0;
end
4'b0100:begin
second_layer_11to8[1] = 1'b0;
second_layer_11to8[0] = 1'b1;
end
4'b0101:begin
second_layer_11to8[1] = 1'b1;
second_layer_11to8[0] = 1'b0;
end
4'b0110:begin
second_layer_11to8[1] = 1'b0;
second_layer_11to8[0] = 1'b0;
end
4'b1000:begin
second_layer_11to8[1] = 1'b1;
second_layer_11to8[0] = 1'b0;
end
4'b1001:begin
second_layer_11to8[1] = 1'b0;
second_layer_11to8[0] = 1'b0;
end
4'b1010:begin
second_layer_11to8[1] = 1'b0;
second_layer_11to8[0] = 1'b1;
end
default: begin // Needed to prevent latches being inferred
second_layer_11to8[1] = 1'b0;
second_layer_11to8[0] = 1'b0;
end
endcase

case (first_layer[14:12])
3'b000:begin
second_layer_14to12[1] = 1'b0;
second_layer_14to12[0] = 1'b0;
end
3'b001:begin
second_layer_14to12[1] = 1'b0;
second_layer_14to12[0] = 1'b1;
end
3'b010:begin
second_layer_14to12[1] = 1'b1;
second_layer_14to12[0] = 1'b0;
end
3'b100:begin
second_layer_14to12[1] = 1'b0;
second_layer_14to12[0] = 1'b1;
end
3'b101:begin
second_layer_14to12[1] = 1'b1;
second_layer_14to12[0] = 1'b0;
end
3'b110:begin
second_layer_14to12[1] = 1'b0;
second_layer_14to12[0] = 1'b0;
end
default: begin // Needed to prevent latches being inferred
second_layer_14to12[1] = 1'b0;
second_layer_14to12[0] = 1'b0;
end
endcase



end //always


always @ (second_layer_7to4 or second_layer_3to0)
begin
case ({second_layer_7to4[1:0],second_layer_3to0[1:0]})
4'b0000:begin
third_layer_7to0[1] = 1'b0;
third_layer_7to0[0] = 1'b0;
end
4'b0001:begin
third_layer_7to0[1] = 1'b0;
third_layer_7to0[0] = 1'b1;
end
4'b0010:begin
third_layer_7to0[1] = 1'b1;
third_layer_7to0[0] = 1'b0;
end
4'b0100:begin
third_layer_7to0[1] = 1'b0;
third_layer_7to0[0] = 1'b1;
end
4'b0101:begin
third_layer_7to0[1] = 1'b1;
third_layer_7to0[0] = 1'b0;
end
4'b0110:begin
third_layer_7to0[1] = 1'b0;
third_layer_7to0[0] = 1'b0;
end
4'b1000:begin
third_layer_7to0[1] = 1'b1;
third_layer_7to0[0] = 1'b0;
end
4'b1001:begin
third_layer_7to0[1] = 1'b0;
third_layer_7to0[0] = 1'b0;
end
4'b1010:begin
third_layer_7to0[1] = 1'b0;
third_layer_7to0[0] = 1'b1;
end
default: begin // Needed to prevent latches being inferred
third_layer_7to0[1] = 1'b0;
third_layer_7to0[0] = 1'b0;
end
endcase
end // always

always @ (second_layer_14to12 or second_layer_11to8)
begin

case ({second_layer_14to12[1:0], second_layer_11to8[1:0]})
4'b0000:begin
third_layer_14to8[1] = 1'b0;
third_layer_14to8[0] = 1'b0;
end
4'b0001:begin
third_layer_14to8[1] = 1'b0;
third_layer_14to8[0] = 1'b1;
end
4'b0010:begin
third_layer_14to8[1] = 1'b1;
third_layer_14to8[0] = 1'b0;
end
4'b0100:begin
third_layer_14to8[1] = 1'b0;
third_layer_14to8[0] = 1'b1;
end
4'b0101:begin
third_layer_14to8[1] = 1'b1;
third_layer_14to8[0] = 1'b0;
end
4'b0110:begin
third_layer_14to8[1] = 1'b0;
third_layer_14to8[0] = 1'b0;
end
4'b1000:begin
third_layer_14to8[1] = 1'b1;
third_layer_14to8[0] = 1'b0;
end
4'b1001:begin
third_layer_14to8[1] = 1'b0;
third_layer_14to8[0] = 1'b0;
end
4'b1010:begin
third_layer_14to8[1] = 1'b0;
third_layer_14to8[0] = 1'b1;
end
default: begin // Needed to prevent latches being inferred
third_layer_14to8[1] = 1'b0;
third_layer_14to8[0] = 1'b0;
end
endcase
end // always


always @ (third_layer_14to8 or third_layer_7to0)
begin

case ({third_layer_14to8[1:0],third_layer_7to0[1:0]})
4'b0000:begin
result_mod3[1] = 1'b0;
result_mod3[0] = 1'b0;
end
4'b0001:begin
result_mod3[1] = 1'b0;
result_mod3[0] = 1'b1;
end
4'b0010:begin
result_mod3[1] = 1'b1;
result_mod3[0] = 1'b0;
end
4'b0100:begin
result_mod3[1] = 1'b0;
result_mod3[0] = 1'b1;
end
4'b0101:begin
result_mod3[1] = 1'b1;
result_mod3[0] = 1'b0;
end
4'b0110:begin
result_mod3[1] = 1'b0;
result_mod3[0] = 1'b0;
end
4'b1000:begin
result_mod3[1] = 1'b1;
result_mod3[0] = 1'b0;
end
4'b1001:begin
result_mod3[1] = 1'b0;
result_mod3[0] = 1'b0;
end
4'b1010:begin
result_mod3[1] = 1'b0;
result_mod3[0] = 1'b1;
end
default: begin // Needed to prevent latches being inferred
result_mod3[1] = 1'b0;
result_mod3[0] = 1'b0;
end
endcase
end // always


// *****************************************************************
// End of compute the modulo3 of reg_to_solve
// *****************************************************************



endmodule // modulo3_15bit_flat

modulo3_16bit_flat.v

//--------------------------------------------------------------------------
// Module : modulo3_16bit_flat
// Full Module Name : modulo3_16bit_flat.v
// Current Version : 1.0
// Version Date : June 8, 2009
//
// Description : Modulo3 Combinatorial Calculation of 16-bit Register
//
//
// No comments here, this is just a flattened, 15-bit modulo-3, so the user
// can see the code structure more clearly without the clutter.
//--------------------------------------------------------------------------


module modulo3_16bit_flat (
// inputs
reg_to_solve,

// outputs
result_mod3
);


//--------------------------------------------------------------------------
// Inputs / Outputs Description
//--------------------------------------------------------------------------

input [15:0] reg_to_solve;
output [1:0] result_mod3;

//--------------------------------------------------------------------------
// Signal Declaration
//--------------------------------------------------------------------------

wire [15:0] first_layer;
reg [1:0] second_layer_3to0;
reg [1:0] second_layer_7to4;
reg [1:0] second_layer_11to8;
reg [1:0] second_layer_15to12;
reg [1:0] third_layer_7to0;
reg [1:0] third_layer_15to8;
reg [1:0] result_mod3;

// *****************************************************************
// Compute the modulo3 of reg_to_solve using combinational logic only
// *****************************************************************

//First examine the reg_to_solve pairs so that:
// 00 -> 00
// 01 -> 01
// 10 -> 10
// 11 -> 00
assign first_layer[0] = (reg_to_solve[1] ^ reg_to_solve[0]) & reg_to_solve[0];
assign first_layer[1] = (reg_to_solve[1] ^ reg_to_solve[0]) & reg_to_solve[1];
assign first_layer[2] = (reg_to_solve[3] ^ reg_to_solve[2]) & reg_to_solve[2];
assign first_layer[3] = (reg_to_solve[3] ^ reg_to_solve[2]) & reg_to_solve[3];
assign first_layer[4] = (reg_to_solve[5] ^ reg_to_solve[4]) & reg_to_solve[4];
assign first_layer[5] = (reg_to_solve[5] ^ reg_to_solve[4]) & reg_to_solve[5];
assign first_layer[6] = (reg_to_solve[7] ^ reg_to_solve[6]) & reg_to_solve[6];
assign first_layer[7] = (reg_to_solve[7] ^ reg_to_solve[6]) & reg_to_solve[7];
assign first_layer[8] = (reg_to_solve[9] ^ reg_to_solve[8]) & reg_to_solve[8];
assign first_layer[9] = (reg_to_solve[9] ^ reg_to_solve[8]) & reg_to_solve[9];
assign first_layer[10] = (reg_to_solve[11] ^ reg_to_solve[10]) & reg_to_solve[10];
assign first_layer[11] = (reg_to_solve[11] ^ reg_to_solve[10]) & reg_to_solve[11];
assign first_layer[12] = (reg_to_solve[13] ^ reg_to_solve[12]) & reg_to_solve[12];
assign first_layer[13] = (reg_to_solve[13] ^ reg_to_solve[12]) & reg_to_solve[13];
assign first_layer[14] = (reg_to_solve[15] ^ reg_to_solve[14]) & reg_to_solve[14];
assign first_layer[15] = (reg_to_solve[15] ^ reg_to_solve[14]) & reg_to_solve[15];

always @ (first_layer)
begin
// nine choices:
// 0000 -> 00
// 0001 -> 01
// 0010 -> 10
// 0100 -> 01
// 0101 -> 10
// 0110 -> 00
// 1000 -> 10
// 1001 -> 00
// 1010 -> 01
case (first_layer[3:0])
4'b0000: begin
second_layer_3to0[1] = 1'b0;
second_layer_3to0[0] = 1'b0;
end
4'b0001: begin
second_layer_3to0[1] = 1'b0;
second_layer_3to0[0] = 1'b1;
end
4'b0010: begin
second_layer_3to0[1] = 1'b1;
second_layer_3to0[0] = 1'b0;
end
4'b0100: begin
second_layer_3to0[1] = 1'b0;
second_layer_3to0[0] = 1'b1;
end
4'b0101: begin
second_layer_3to0[1] = 1'b1;
second_layer_3to0[0] = 1'b0;
end
4'b0110: begin
second_layer_3to0[1] = 1'b0;
second_layer_3to0[0] = 1'b0;
end
4'b1000: begin
second_layer_3to0[1] = 1'b1;
second_layer_3to0[0] = 1'b0;
end
4'b1001: begin
second_layer_3to0[1] = 1'b0;
second_layer_3to0[0] = 1'b0;
end
4'b1010: begin
second_layer_3to0[1] = 1'b0;
second_layer_3to0[0] = 1'b1;
end
default: begin // Needed to prevent latches being inferred
second_layer_3to0[1] = 1'b0;
second_layer_3to0[0] = 1'b0;
end
endcase

case (first_layer[7:4])
4'b0000:begin
second_layer_7to4[1] = 1'b0;
second_layer_7to4[0] = 1'b0;
end
4'b0001:begin
second_layer_7to4[1] = 1'b0;
second_layer_7to4[0] = 1'b1;
end
4'b0010:begin
second_layer_7to4[1] = 1'b1;
second_layer_7to4[0] = 1'b0;
end
4'b0100:begin
second_layer_7to4[1] = 1'b0;
second_layer_7to4[0] = 1'b1;
end
4'b0101:begin
second_layer_7to4[1] = 1'b1;
second_layer_7to4[0] = 1'b0;
end
4'b0110:begin
second_layer_7to4[1] = 1'b0;
second_layer_7to4[0] = 1'b0;
end
4'b1000:begin
second_layer_7to4[1] = 1'b1;
second_layer_7to4[0] = 1'b0;
end
4'b1001:begin
second_layer_7to4[1] = 1'b0;
second_layer_7to4[0] = 1'b0;
end
4'b1010:begin
second_layer_7to4[1] = 1'b0;
second_layer_7to4[0] = 1'b1;
end
default: begin // Needed to prevent latches being inferred
second_layer_7to4[1] = 1'b0;
second_layer_7to4[0] = 1'b0;
end
endcase


case (first_layer[11:8])
4'b0000:begin
second_layer_11to8[1] = 1'b0;
second_layer_11to8[0] = 1'b0;
end
4'b0001:begin
second_layer_11to8[1] = 1'b0;
second_layer_11to8[0] = 1'b1;
end
4'b0010:begin
second_layer_11to8[1] = 1'b1;
second_layer_11to8[0] = 1'b0;
end
4'b0100:begin
second_layer_11to8[1] = 1'b0;
second_layer_11to8[0] = 1'b1;
end
4'b0101:begin
second_layer_11to8[1] = 1'b1;
second_layer_11to8[0] = 1'b0;
end
4'b0110:begin
second_layer_11to8[1] = 1'b0;
second_layer_11to8[0] = 1'b0;
end
4'b1000:begin
second_layer_11to8[1] = 1'b1;
second_layer_11to8[0] = 1'b0;
end
4'b1001:begin
second_layer_11to8[1] = 1'b0;
second_layer_11to8[0] = 1'b0;
end
4'b1010:begin
second_layer_11to8[1] = 1'b0;
second_layer_11to8[0] = 1'b1;
end
default: begin // Needed to prevent latches being inferred
second_layer_11to8[1] = 1'b0;
second_layer_11to8[0] = 1'b0;
end
endcase

case (first_layer[15:12])
4'b0000:begin
second_layer_15to12[1] = 1'b0;
second_layer_15to12[0] = 1'b0;
end
4'b0001:begin
second_layer_15to12[1] = 1'b0;
second_layer_15to12[0] = 1'b1;
end
4'b0010:begin
second_layer_15to12[1] = 1'b1;
second_layer_15to12[0] = 1'b0;
end
4'b0100:begin
second_layer_15to12[1] = 1'b0;
second_layer_15to12[0] = 1'b1;
end
4'b0101:begin
second_layer_15to12[1] = 1'b1;
second_layer_15to12[0] = 1'b0;
end
4'b0110:begin
second_layer_15to12[1] = 1'b0;
second_layer_15to12[0] = 1'b0;
end
4'b1000:begin
second_layer_15to12[1] = 1'b1;
second_layer_15to12[0] = 1'b0;
end
4'b1001:begin
second_layer_15to12[1] = 1'b0;
second_layer_15to12[0] = 1'b0;
end
4'b1010:begin
second_layer_15to12[1] = 1'b0;
second_layer_15to12[0] = 1'b1;
end
default: begin // Needed to prevent latches being inferred
second_layer_15to12[1] = 1'b0;
second_layer_15to12[0] = 1'b0;
end
endcase



end //always


always @ (second_layer_7to4 or second_layer_3to0)
begin
case ({second_layer_7to4[1:0],second_layer_3to0[1:0]})
4'b0000:begin
third_layer_7to0[1] = 1'b0;
third_layer_7to0[0] = 1'b0;
end
4'b0001:begin
third_layer_7to0[1] = 1'b0;
third_layer_7to0[0] = 1'b1;
end
4'b0010:begin
third_layer_7to0[1] = 1'b1;
third_layer_7to0[0] = 1'b0;
end
4'b0100:begin
third_layer_7to0[1] = 1'b0;
third_layer_7to0[0] = 1'b1;
end
4'b0101:begin
third_layer_7to0[1] = 1'b1;
third_layer_7to0[0] = 1'b0;
end
4'b0110:begin
third_layer_7to0[1] = 1'b0;
third_layer_7to0[0] = 1'b0;
end
4'b1000:begin
third_layer_7to0[1] = 1'b1;
third_layer_7to0[0] = 1'b0;
end
4'b1001:begin
third_layer_7to0[1] = 1'b0;
third_layer_7to0[0] = 1'b0;
end
4'b1010:begin
third_layer_7to0[1] = 1'b0;
third_layer_7to0[0] = 1'b1;
end
default: begin // Needed to prevent latches being inferred
third_layer_7to0[1] = 1'b0;
third_layer_7to0[0] = 1'b0;
end
endcase
end // always

always @ (second_layer_15to12 or second_layer_11to8)
begin

case ({second_layer_15to12[1:0], second_layer_11to8[1:0]})
4'b0000:begin
third_layer_15to8[1] = 1'b0;
third_layer_15to8[0] = 1'b0;
end
4'b0001:begin
third_layer_15to8[1] = 1'b0;
third_layer_15to8[0] = 1'b1;
end
4'b0010:begin
third_layer_15to8[1] = 1'b1;
third_layer_15to8[0] = 1'b0;
end
4'b0100:begin
third_layer_15to8[1] = 1'b0;
third_layer_15to8[0] = 1'b1;
end
4'b0101:begin
third_layer_15to8[1] = 1'b1;
third_layer_15to8[0] = 1'b0;
end
4'b0110:begin
third_layer_15to8[1] = 1'b0;
third_layer_15to8[0] = 1'b0;
end
4'b1000:begin
third_layer_15to8[1] = 1'b1;
third_layer_15to8[0] = 1'b0;
end
4'b1001:begin
third_layer_15to8[1] = 1'b0;
third_layer_15to8[0] = 1'b0;
end
4'b1010:begin
third_layer_15to8[1] = 1'b0;
third_layer_15to8[0] = 1'b1;
end
default: begin // Needed to prevent latches being inferred
third_layer_15to8[1] = 1'b0;
third_layer_15to8[0] = 1'b0;
end
endcase
end // always


always @ (third_layer_15to8 or third_layer_7to0)
begin

case ({third_layer_15to8[1:0],third_layer_7to0[1:0]})
4'b0000:begin
result_mod3[1] = 1'b0;
result_mod3[0] = 1'b0;
end
4'b0001:begin
result_mod3[1] = 1'b0;
result_mod3[0] = 1'b1;
end
4'b0010:begin
result_mod3[1] = 1'b1;
result_mod3[0] = 1'b0;
end
4'b0100:begin
result_mod3[1] = 1'b0;
result_mod3[0] = 1'b1;
end
4'b0101:begin
result_mod3[1] = 1'b1;
result_mod3[0] = 1'b0;
end
4'b0110:begin
result_mod3[1] = 1'b0;
result_mod3[0] = 1'b0;
end
4'b1000:begin
result_mod3[1] = 1'b1;
result_mod3[0] = 1'b0;
end
4'b1001:begin
result_mod3[1] = 1'b0;
result_mod3[0] = 1'b0;
end
4'b1010:begin
result_mod3[1] = 1'b0;
result_mod3[0] = 1'b1;
end
default: begin // Needed to prevent latches being inferred
result_mod3[1] = 1'b0;
result_mod3[0] = 1'b0;
end
endcase
end // always


// *****************************************************************
// End of compute the modulo3 of reg_to_solve
// *****************************************************************



endmodule // modulo3_16bit

modulo3_36bit_flat.v

//--------------------------------------------------------------------------
// Module : modulo3_36bit_flat
// Full Module Name : modulo3_36bit_flat.v
// Current Version : 1.0
// Version Date : June 3, 2009
//
// Description : Modulo3 Combinatorial Calculation of 36-bit Register
//
//
// No comments here, this is just a flattened, 36-bit modulo-3, so the user
// can see the code structure more clearly without the clutter.
//--------------------------------------------------------------------------


module modulo3_36bit_flat (
// inputs
reg_to_solve,

// outputs
result_mod3
);


//--------------------------------------------------------------------------
// Inputs / Outputs Description
//--------------------------------------------------------------------------

input [35:0] reg_to_solve;
output [1:0] result_mod3;

//--------------------------------------------------------------------------
// Signal Declaration
//--------------------------------------------------------------------------

wire [35:0] first_layer;
reg [1:0] second_layer_3to0;
reg [1:0] second_layer_7to4;
reg [1:0] second_layer_11to8;
reg [1:0] second_layer_15to12;
reg [1:0] second_layer_19to16;
reg [1:0] second_layer_23to20;
reg [1:0] second_layer_27to24;
reg [1:0] second_layer_31to28;
reg [1:0] second_layer_35to32;
reg [1:0] third_layer_7to0;
reg [1:0] third_layer_15to8;
reg [1:0] third_layer_23to16;
reg [1:0] third_layer_31to24;
reg [1:0] third_layer_35to32;
reg [1:0] forth_layer_15to0;
reg [1:0] forth_layer_31to16;
reg [1:0] fifth_layer_31to0;
reg [1:0] result_mod3;

// *****************************************************************
// Compute the modulo3 of reg_to_solve using combinational logic only
// *****************************************************************

//First examine the reg_to_solve pairs so that:
// 00 -> 00
// 01 -> 01
// 10 -> 10
// 11 -> 00
assign first_layer[0] = (reg_to_solve[1] ^ reg_to_solve[0]) & reg_to_solve[0];
assign first_layer[1] = (reg_to_solve[1] ^ reg_to_solve[0]) & reg_to_solve[1];
assign first_layer[2] = (reg_to_solve[3] ^ reg_to_solve[2]) & reg_to_solve[2];
assign first_layer[3] = (reg_to_solve[3] ^ reg_to_solve[2]) & reg_to_solve[3];
assign first_layer[4] = (reg_to_solve[5] ^ reg_to_solve[4]) & reg_to_solve[4];
assign first_layer[5] = (reg_to_solve[5] ^ reg_to_solve[4]) & reg_to_solve[5];
assign first_layer[6] = (reg_to_solve[7] ^ reg_to_solve[6]) & reg_to_solve[6];
assign first_layer[7] = (reg_to_solve[7] ^ reg_to_solve[6]) & reg_to_solve[7];
assign first_layer[8] = (reg_to_solve[9] ^ reg_to_solve[8]) & reg_to_solve[8];
assign first_layer[9] = (reg_to_solve[9] ^ reg_to_solve[8]) & reg_to_solve[9];
assign first_layer[10] = (reg_to_solve[11] ^ reg_to_solve[10]) & reg_to_solve[10];
assign first_layer[11] = (reg_to_solve[11] ^ reg_to_solve[10]) & reg_to_solve[11];
assign first_layer[12] = (reg_to_solve[13] ^ reg_to_solve[12]) & reg_to_solve[12];
assign first_layer[13] = (reg_to_solve[13] ^ reg_to_solve[12]) & reg_to_solve[13];
assign first_layer[14] = (reg_to_solve[15] ^ reg_to_solve[14]) & reg_to_solve[14];
assign first_layer[15] = (reg_to_solve[15] ^ reg_to_solve[14]) & reg_to_solve[15];
assign first_layer[16] = (reg_to_solve[17] ^ reg_to_solve[16]) & reg_to_solve[16];
assign first_layer[17] = (reg_to_solve[17] ^ reg_to_solve[16]) & reg_to_solve[17];
assign first_layer[18] = (reg_to_solve[19] ^ reg_to_solve[18]) & reg_to_solve[18];
assign first_layer[19] = (reg_to_solve[19] ^ reg_to_solve[18]) & reg_to_solve[19];
assign first_layer[20] = (reg_to_solve[21] ^ reg_to_solve[20]) & reg_to_solve[20];
assign first_layer[21] = (reg_to_solve[21] ^ reg_to_solve[20]) & reg_to_solve[21];
assign first_layer[22] = (reg_to_solve[23] ^ reg_to_solve[22]) & reg_to_solve[22];
assign first_layer[23] = (reg_to_solve[23] ^ reg_to_solve[22]) & reg_to_solve[23];
assign first_layer[24] = (reg_to_solve[25] ^ reg_to_solve[24]) & reg_to_solve[24];
assign first_layer[25] = (reg_to_solve[25] ^ reg_to_solve[24]) & reg_to_solve[25];
assign first_layer[26] = (reg_to_solve[27] ^ reg_to_solve[26]) & reg_to_solve[26];
assign first_layer[27] = (reg_to_solve[27] ^ reg_to_solve[26]) & reg_to_solve[27];
assign first_layer[28] = (reg_to_solve[29] ^ reg_to_solve[28]) & reg_to_solve[28];
assign first_layer[29] = (reg_to_solve[29] ^ reg_to_solve[28]) & reg_to_solve[29];
assign first_layer[30] = (reg_to_solve[31] ^ reg_to_solve[30]) & reg_to_solve[30];
assign first_layer[31] = (reg_to_solve[31] ^ reg_to_solve[30]) & reg_to_solve[31];
assign first_layer[32] = (reg_to_solve[33] ^ reg_to_solve[32]) & reg_to_solve[32];
assign first_layer[33] = (reg_to_solve[33] ^ reg_to_solve[32]) & reg_to_solve[33];
assign first_layer[34] = (reg_to_solve[35] ^ reg_to_solve[34]) & reg_to_solve[34];
assign first_layer[35] = (reg_to_solve[35] ^ reg_to_solve[34]) & reg_to_solve[35];

always @ (first_layer)
begin
// nine choices:
// 0000 -> 00
// 0001 -> 01
// 0010 -> 10
// 0100 -> 01
// 0101 -> 10
// 0110 -> 00
// 1000 -> 10
// 1001 -> 00
// 1010 -> 01
case (first_layer[3:0])
4'b0000: begin
second_layer_3to0[1] = 1'b0;
second_layer_3to0[0] = 1'b0;
end
4'b0001: begin
second_layer_3to0[1] = 1'b0;
second_layer_3to0[0] = 1'b1;
end
4'b0010: begin
second_layer_3to0[1] = 1'b1;
second_layer_3to0[0] = 1'b0;
end
4'b0100: begin
second_layer_3to0[1] = 1'b0;
second_layer_3to0[0] = 1'b1;
end
4'b0101: begin
second_layer_3to0[1] = 1'b1;
second_layer_3to0[0] = 1'b0;
end
4'b0110: begin
second_layer_3to0[1] = 1'b0;
second_layer_3to0[0] = 1'b0;
end
4'b1000: begin
second_layer_3to0[1] = 1'b1;
second_layer_3to0[0] = 1'b0;
end
4'b1001: begin
second_layer_3to0[1] = 1'b0;
second_layer_3to0[0] = 1'b0;
end
4'b1010: begin
second_layer_3to0[1] = 1'b0;
second_layer_3to0[0] = 1'b1;
end
default: begin
second_layer_3to0[1] = 1'b0;
second_layer_3to0[0] = 1'b0;
end
endcase

case (first_layer[7:4])
4'b0000:begin
second_layer_7to4[1] = 1'b0;
second_layer_7to4[0] = 1'b0;
end
4'b0001:begin
second_layer_7to4[1] = 1'b0;
second_layer_7to4[0] = 1'b1;
end
4'b0010:begin
second_layer_7to4[1] = 1'b1;
second_layer_7to4[0] = 1'b0;
end
4'b0100:begin
second_layer_7to4[1] = 1'b0;
second_layer_7to4[0] = 1'b1;
end
4'b0101:begin
second_layer_7to4[1] = 1'b1;
second_layer_7to4[0] = 1'b0;
end
4'b0110:begin
second_layer_7to4[1] = 1'b0;
second_layer_7to4[0] = 1'b0;
end
4'b1000:begin
second_layer_7to4[1] = 1'b1;
second_layer_7to4[0] = 1'b0;
end
4'b1001:begin
second_layer_7to4[1] = 1'b0;
second_layer_7to4[0] = 1'b0;
end
4'b1010:begin
second_layer_7to4[1] = 1'b0;
second_layer_7to4[0] = 1'b1;
end
default: begin
second_layer_7to4[1] = 1'b0;
second_layer_7to4[0] = 1'b0;
end
endcase


case (first_layer[11:8])
4'b0000:begin
second_layer_11to8[1] = 1'b0;
second_layer_11to8[0] = 1'b0;
end
4'b0001:begin
second_layer_11to8[1] = 1'b0;
second_layer_11to8[0] = 1'b1;
end
4'b0010:begin
second_layer_11to8[1] = 1'b1;
second_layer_11to8[0] = 1'b0;
end
4'b0100:begin
second_layer_11to8[1] = 1'b0;
second_layer_11to8[0] = 1'b1;
end
4'b0101:begin
second_layer_11to8[1] = 1'b1;
second_layer_11to8[0] = 1'b0;
end
4'b0110:begin
second_layer_11to8[1] = 1'b0;
second_layer_11to8[0] = 1'b0;
end
4'b1000:begin
second_layer_11to8[1] = 1'b1;
second_layer_11to8[0] = 1'b0;
end
4'b1001:begin
second_layer_11to8[1] = 1'b0;
second_layer_11to8[0] = 1'b0;
end
4'b1010:begin
second_layer_11to8[1] = 1'b0;
second_layer_11to8[0] = 1'b1;
end
default: begin
second_layer_11to8[1] = 1'b0;
second_layer_11to8[0] = 1'b0;
end
endcase


case (first_layer[15:12])
4'b0000:begin
second_layer_15to12[1] = 1'b0;
second_layer_15to12[0] = 1'b0;
end
4'b0001:begin
second_layer_15to12[1] = 1'b0;
second_layer_15to12[0] = 1'b1;
end
4'b0010:begin
second_layer_15to12[1] = 1'b1;
second_layer_15to12[0] = 1'b0;
end
4'b0100:begin
second_layer_15to12[1] = 1'b0;
second_layer_15to12[0] = 1'b1;
end
4'b0101:begin
second_layer_15to12[1] = 1'b1;
second_layer_15to12[0] = 1'b0;
end
4'b0110:begin
second_layer_15to12[1] = 1'b0;
second_layer_15to12[0] = 1'b0;
end
4'b1000:begin
second_layer_15to12[1] = 1'b1;
second_layer_15to12[0] = 1'b0;
end
4'b1001:begin
second_layer_15to12[1] = 1'b0;
second_layer_15to12[0] = 1'b0;
end
4'b1010:begin
second_layer_15to12[1] = 1'b0;
second_layer_15to12[0] = 1'b1;
end
default: begin
second_layer_15to12[1] = 1'b0;
second_layer_15to12[0] = 1'b0;
end
endcase

case (first_layer[19:16])
4'b0000: begin
second_layer_19to16[1] = 1'b0;
second_layer_19to16[0] = 1'b0;
end
4'b0001: begin
second_layer_19to16[1] = 1'b0;
second_layer_19to16[0] = 1'b1;
end
4'b0010: begin
second_layer_19to16[1] = 1'b1;
second_layer_19to16[0] = 1'b0;
end
4'b0100: begin
second_layer_19to16[1] = 1'b0;
second_layer_19to16[0] = 1'b1;
end
4'b0101: begin
second_layer_19to16[1] = 1'b1;
second_layer_19to16[0] = 1'b0;
end
4'b0110: begin
second_layer_19to16[1] = 1'b0;
second_layer_19to16[0] = 1'b0;
end
4'b1000: begin
second_layer_19to16[1] = 1'b1;
second_layer_19to16[0] = 1'b0;
end
4'b1001: begin
second_layer_19to16[1] = 1'b0;
second_layer_19to16[0] = 1'b0;
end
4'b1010: begin
second_layer_19to16[1] = 1'b0;
second_layer_19to16[0] = 1'b1;
end
default: begin
second_layer_19to16[1] = 1'b0;
second_layer_19to16[0] = 1'b0;
end
endcase

case (first_layer[23:20])
4'b0000: begin
second_layer_23to20[1] = 1'b0;
second_layer_23to20[0] = 1'b0;
end
4'b0001: begin
second_layer_23to20[1] = 1'b0;
second_layer_23to20[0] = 1'b1;
end
4'b0010: begin
second_layer_23to20[1] = 1'b1;
second_layer_23to20[0] = 1'b0;
end
4'b0100: begin
second_layer_23to20[1] = 1'b0;
second_layer_23to20[0] = 1'b1;
end
4'b0101: begin
second_layer_23to20[1] = 1'b1;
second_layer_23to20[0] = 1'b0;
end
4'b0110: begin
second_layer_23to20[1] = 1'b0;
second_layer_23to20[0] = 1'b0;
end
4'b1000: begin
second_layer_23to20[1] = 1'b1;
second_layer_23to20[0] = 1'b0;
end
4'b1001: begin
second_layer_23to20[1] = 1'b0;
second_layer_23to20[0] = 1'b0;
end
4'b1010: begin
second_layer_23to20[1] = 1'b0;
second_layer_23to20[0] = 1'b1;
end
default: begin
second_layer_23to20[1] = 1'b0;
second_layer_23to20[0] = 1'b0;
end
endcase

case (first_layer[27:24])
4'b0000: begin
second_layer_27to24[1] = 1'b0;
second_layer_27to24[0] = 1'b0;
end
4'b0001: begin
second_layer_27to24[1] = 1'b0;
second_layer_27to24[0] = 1'b1;
end
4'b0010: begin
second_layer_27to24[1] = 1'b1;
second_layer_27to24[0] = 1'b0;
end
4'b0100: begin
second_layer_27to24[1] = 1'b0;
second_layer_27to24[0] = 1'b1;
end
4'b0101: begin
second_layer_27to24[1] = 1'b1;
second_layer_27to24[0] = 1'b0;
end
4'b0110: begin
second_layer_27to24[1] = 1'b0;
second_layer_27to24[0] = 1'b0;
end
4'b1000: begin
second_layer_27to24[1] = 1'b1;
second_layer_27to24[0] = 1'b0;
end
4'b1001: begin
second_layer_27to24[1] = 1'b0;
second_layer_27to24[0] = 1'b0;
end
4'b1010: begin
second_layer_27to24[1] = 1'b0;
second_layer_27to24[0] = 1'b1;
end
default: begin
second_layer_27to24[1] = 1'b0;
second_layer_27to24[0] = 1'b0;
end
endcase

case (first_layer[31:28])
4'b0000: begin
second_layer_31to28[1] = 1'b0;
second_layer_31to28[0] = 1'b0;
end
4'b0001: begin
second_layer_31to28[1] = 1'b0;
second_layer_31to28[0] = 1'b1;
end
4'b0010: begin
second_layer_31to28[1] = 1'b1;
second_layer_31to28[0] = 1'b0;
end
4'b0100: begin
second_layer_31to28[1] = 1'b0;
second_layer_31to28[0] = 1'b1;
end
4'b0101: begin
second_layer_31to28[1] = 1'b1;
second_layer_31to28[0] = 1'b0;
end
4'b0110: begin
second_layer_31to28[1] = 1'b0;
second_layer_31to28[0] = 1'b0;
end
4'b1000: begin
second_layer_31to28[1] = 1'b1;
second_layer_31to28[0] = 1'b0;
end
4'b1001: begin
second_layer_31to28[1] = 1'b0;
second_layer_31to28[0] = 1'b0;
end
4'b1010: begin
second_layer_31to28[1] = 1'b0;
second_layer_31to28[0] = 1'b1;
end
default: begin
second_layer_31to28[1] = 1'b0;
second_layer_31to28[0] = 1'b0;
end
endcase

case (first_layer[35:32])
4'b0000: begin
second_layer_35to32[1] = 1'b0;
second_layer_35to32[0] = 1'b0;
end
4'b0001: begin
second_layer_35to32[1] = 1'b0;
second_layer_35to32[0] = 1'b1;
end
4'b0010: begin
second_layer_35to32[1] = 1'b1;
second_layer_35to32[0] = 1'b0;
end
4'b0100: begin
second_layer_35to32[1] = 1'b0;
second_layer_35to32[0] = 1'b1;
end
4'b0101: begin
second_layer_35to32[1] = 1'b1;
second_layer_35to32[0] = 1'b0;
end
4'b0110: begin
second_layer_35to32[1] = 1'b0;
second_layer_35to32[0] = 1'b0;
end
4'b1000: begin
second_layer_35to32[1] = 1'b1;
second_layer_35to32[0] = 1'b0;
end
4'b1001: begin
second_layer_35to32[1] = 1'b0;
second_layer_35to32[0] = 1'b0;
end
4'b1010: begin
second_layer_35to32[1] = 1'b0;
second_layer_35to32[0] = 1'b1;
end
default: begin
second_layer_35to32[1] = 1'b0;
second_layer_35to32[0] = 1'b0;
end
endcase

end //always


always @ (second_layer_7to4 or second_layer_3to0)
begin
case ({second_layer_7to4[1:0],second_layer_3to0[1:0]})
4'b0000:begin
third_layer_7to0[1] = 1'b0;
third_layer_7to0[0] = 1'b0;
end
4'b0001:begin
third_layer_7to0[1] = 1'b0;
third_layer_7to0[0] = 1'b1;
end
4'b0010:begin
third_layer_7to0[1] = 1'b1;
third_layer_7to0[0] = 1'b0;
end
4'b0100:begin
third_layer_7to0[1] = 1'b0;
third_layer_7to0[0] = 1'b1;
end
4'b0101:begin
third_layer_7to0[1] = 1'b1;
third_layer_7to0[0] = 1'b0;
end
4'b0110:begin
third_layer_7to0[1] = 1'b0;
third_layer_7to0[0] = 1'b0;
end
4'b1000:begin
third_layer_7to0[1] = 1'b1;
third_layer_7to0[0] = 1'b0;
end
4'b1001:begin
third_layer_7to0[1] = 1'b0;
third_layer_7to0[0] = 1'b0;
end
4'b1010:begin
third_layer_7to0[1] = 1'b0;
third_layer_7to0[0] = 1'b1;
end
default:begin
third_layer_7to0[1] = 1'b0;
third_layer_7to0[0] = 1'b0;
end
endcase
end // always

always @ (second_layer_15to12 or second_layer_11to8)
begin

case ({second_layer_15to12[1:0],second_layer_11to8[1:0]})
4'b0000:begin
third_layer_15to8[1] = 1'b0;
third_layer_15to8[0] = 1'b0;
end
4'b0001:begin
third_layer_15to8[1] = 1'b0;
third_layer_15to8[0] = 1'b1;
end
4'b0010:begin
third_layer_15to8[1] = 1'b1;
third_layer_15to8[0] = 1'b0;
end
4'b0100:begin
third_layer_15to8[1] = 1'b0;
third_layer_15to8[0] = 1'b1;
end
4'b0101:begin
third_layer_15to8[1] = 1'b1;
third_layer_15to8[0] = 1'b0;
end
4'b0110:begin
third_layer_15to8[1] = 1'b0;
third_layer_15to8[0] = 1'b0;
end
4'b1000:begin
third_layer_15to8[1] = 1'b1;
third_layer_15to8[0] = 1'b0;
end
4'b1001:begin
third_layer_15to8[1] = 1'b0;
third_layer_15to8[0] = 1'b0;
end
4'b1010:begin
third_layer_15to8[1] = 1'b0;
third_layer_15to8[0] = 1'b1;
end
default:begin
third_layer_15to8[1] = 1'b0;
third_layer_15to8[0] = 1'b0;
end
endcase
end // always


always @ (second_layer_23to20 or second_layer_19to16)
begin

case ({second_layer_23to20[1:0],second_layer_19to16[1:0]})
4'b0000:begin
third_layer_23to16[1] = 1'b0;
third_layer_23to16[0] = 1'b0;
end
4'b0001:begin
third_layer_23to16[1] = 1'b0;
third_layer_23to16[0] = 1'b1;
end
4'b0010:begin
third_layer_23to16[1] = 1'b1;
third_layer_23to16[0] = 1'b0;
end
4'b0100:begin
third_layer_23to16[1] = 1'b0;
third_layer_23to16[0] = 1'b1;
end
4'b0101:begin
third_layer_23to16[1] = 1'b1;
third_layer_23to16[0] = 1'b0;
end
4'b0110:begin
third_layer_23to16[1] = 1'b0;
third_layer_23to16[0] = 1'b0;
end
4'b1000:begin
third_layer_23to16[1] = 1'b1;
third_layer_23to16[0] = 1'b0;
end
4'b1001:begin
third_layer_23to16[1] = 1'b0;
third_layer_23to16[0] = 1'b0;
end
4'b1010:begin
third_layer_23to16[1] = 1'b0;
third_layer_23to16[0] = 1'b1;
end
default:begin
third_layer_23to16[1] = 1'b0;
third_layer_23to16[0] = 1'b0;
end
endcase
end // always



always @ (second_layer_31to28 or second_layer_27to24)
begin

case ({second_layer_31to28[1:0],second_layer_27to24[1:0]})
4'b0000:begin
third_layer_31to24[1] = 1'b0;
third_layer_31to24[0] = 1'b0;
end
4'b0001:begin
third_layer_31to24[1] = 1'b0;
third_layer_31to24[0] = 1'b1;
end
4'b0010:begin
third_layer_31to24[1] = 1'b1;
third_layer_31to24[0] = 1'b0;
end
4'b0100:begin
third_layer_31to24[1] = 1'b0;
third_layer_31to24[0] = 1'b1;
end
4'b0101:begin
third_layer_31to24[1] = 1'b1;
third_layer_31to24[0] = 1'b0;
end
4'b0110:begin
third_layer_31to24[1] = 1'b0;
third_layer_31to24[0] = 1'b0;
end
4'b1000:begin
third_layer_31to24[1] = 1'b1;
third_layer_31to24[0] = 1'b0;
end
4'b1001:begin
third_layer_31to24[1] = 1'b0;
third_layer_31to24[0] = 1'b0;
end
4'b1010:begin
third_layer_31to24[1] = 1'b0;
third_layer_31to24[0] = 1'b1;
end
default:begin
third_layer_31to24[1] = 1'b0;
third_layer_31to24[0] = 1'b0;
end
endcase
end // always




always @ (third_layer_15to8 or third_layer_7to0)
begin

case ({third_layer_15to8[1:0],third_layer_7to0[1:0]})
4'b0000:begin
forth_layer_15to0[1] = 1'b0;
forth_layer_15to0[0] = 1'b0;
end
4'b0001:begin
forth_layer_15to0[1] = 1'b0;
forth_layer_15to0[0] = 1'b1;
end
4'b0010:begin
forth_layer_15to0[1] = 1'b1;
forth_layer_15to0[0] = 1'b0;
end
4'b0100:begin
forth_layer_15to0[1] = 1'b0;
forth_layer_15to0[0] = 1'b1;
end
4'b0101:begin
forth_layer_15to0[1] = 1'b1;
forth_layer_15to0[0] = 1'b0;
end
4'b0110:begin
forth_layer_15to0[1] = 1'b0;
forth_layer_15to0[0] = 1'b0;
end
4'b1000:begin
forth_layer_15to0[1] = 1'b1;
forth_layer_15to0[0] = 1'b0;
end
4'b1001:begin
forth_layer_15to0[1] = 1'b0;
forth_layer_15to0[0] = 1'b0;
end
4'b1010:begin
forth_layer_15to0[1] = 1'b0;
forth_layer_15to0[0] = 1'b1;
end
default:begin
forth_layer_15to0[1] = 1'b0;
forth_layer_15to0[0] = 1'b0;
end
endcase
end // always


always @ (third_layer_31to24 or third_layer_23to16)
begin

case ({third_layer_31to24[1:0],third_layer_23to16[1:0]})
4'b0000:begin
forth_layer_31to16[1] = 1'b0;
forth_layer_31to16[0] = 1'b0;
end
4'b0001:begin
forth_layer_31to16[1] = 1'b0;
forth_layer_31to16[0] = 1'b1;
end
4'b0010:begin
forth_layer_31to16[1] = 1'b1;
forth_layer_31to16[0] = 1'b0;
end
4'b0100:begin
forth_layer_31to16[1] = 1'b0;
forth_layer_31to16[0] = 1'b1;
end
4'b0101:begin
forth_layer_31to16[1] = 1'b1;
forth_layer_31to16[0] = 1'b0;
end
4'b0110:begin
forth_layer_31to16[1] = 1'b0;
forth_layer_31to16[0] = 1'b0;
end
4'b1000:begin
forth_layer_31to16[1] = 1'b1;
forth_layer_31to16[0] = 1'b0;
end
4'b1001:begin
forth_layer_31to16[1] = 1'b0;
forth_layer_31to16[0] = 1'b0;
end
4'b1010:begin
forth_layer_31to16[1] = 1'b0;
forth_layer_31to16[0] = 1'b1;
end
default:begin
forth_layer_31to16[1] = 1'b0;
forth_layer_31to16[0] = 1'b0;
end
endcase
end // always


always @ (forth_layer_31to16 or forth_layer_15to0)
begin

case ({forth_layer_31to16[1:0],forth_layer_15to0[1:0]})
4'b0000:begin
fifth_layer_31to0[1] = 1'b0;
fifth_layer_31to0[0] = 1'b0;
end
4'b0001:begin
fifth_layer_31to0[1] = 1'b0;
fifth_layer_31to0[0] = 1'b1;
end
4'b0010:begin
fifth_layer_31to0[1] = 1'b1;
fifth_layer_31to0[0] = 1'b0;
end
4'b0100:begin
fifth_layer_31to0[1] = 1'b0;
fifth_layer_31to0[0] = 1'b1;
end
4'b0101:begin
fifth_layer_31to0[1] = 1'b1;
fifth_layer_31to0[0] = 1'b0;
end
4'b0110:begin
fifth_layer_31to0[1] = 1'b0;
fifth_layer_31to0[0] = 1'b0;
end
4'b1000:begin
fifth_layer_31to0[1] = 1'b1;
fifth_layer_31to0[0] = 1'b0;
end
4'b1001:begin
fifth_layer_31to0[1] = 1'b0;
fifth_layer_31to0[0] = 1'b0;
end
4'b1010:begin
fifth_layer_31to0[1] = 1'b0;
fifth_layer_31to0[0] = 1'b1;
end
default:begin
fifth_layer_31to0[1] = 1'b0;
fifth_layer_31to0[0] = 1'b0;
end
endcase
end // always



always @ (second_layer_35to32 or fifth_layer_31to0)
begin

case ({second_layer_35to32[1:0],fifth_layer_31to0[1:0]})
4'b0000:begin
result_mod3[1] = 1'b0;
result_mod3[0] = 1'b0;
end
4'b0001:begin
result_mod3[1] = 1'b0;
result_mod3[0] = 1'b1;
end
4'b0010:begin
result_mod3[1] = 1'b1;
result_mod3[0] = 1'b0;
end
4'b0100:begin
result_mod3[1] = 1'b0;
result_mod3[0] = 1'b1;
end
4'b0101:begin
result_mod3[1] = 1'b1;
result_mod3[0] = 1'b0;
end
4'b0110:begin
result_mod3[1] = 1'b0;
result_mod3[0] = 1'b0;
end
4'b1000:begin
result_mod3[1] = 1'b1;
result_mod3[0] = 1'b0;
end
4'b1001:begin
result_mod3[1] = 1'b0;
result_mod3[0] = 1'b0;
end
4'b1010:begin
result_mod3[1] = 1'b0;
result_mod3[0] = 1'b1;
end
default:begin
result_mod3[1] = 1'b0;
result_mod3[0] = 1'b0;
end
endcase
end // always




// *****************************************************************
// End of compute the modulo3 of reg_to_solve
// *****************************************************************



endmodule // modulo3_36bit_flat

readme.txt

Readme.txt, June 11, 2009

module3_Nbit.v
This module computes the 2-bit modulo-3 (%3) for registers up to 64 bits in length. It does
this with three to six levels of combinational logic, using no registers, and can in less
than 10ns.

This is the only file you need to implement, just select 'define bitsize from 3 to 64, inclusive.
Your synthesis tool will eliminate all unused bus inputs above bitsize. There is also
one coding coverup depending on whether bitsize is even or odd.

There is one big comment block in module3_Nbit.v. It details the theory, simulation, synthesis
and timing results in Xilinx virtex5 for various choices of bitsize. Read this comment block
first.

If you want to simulate, use tb_modulo3.v and (for ModelSim users) sim.do and wave.do

I have provides two .bmp showing my simulation results for bitsize = 47.

I have provided hand-edited examples for bitsize = 12,13,14,15,16 and 36. If your synthesis does
not support "genvar" you will have to hand-edit to get the bitsize you want. I verified that
the Xilinx XST synthesizer gives identical implementations of the hand-edit versions and the
module_Nbit.v version. I also include modulo3_Nbit.ucf for Xilinx place & route and a command
line for those who prefer cmd line over GUI.

sim.do

vsim work.tb_modulo3 -L XilinxCoreLib_ver -L unisims_ver

wave.do

onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -color {Medium Orchid} -format Logic /tb_modulo3/clk
add wave -noupdate -color {Medium Orchid} -format Logic /tb_modulo3/reset_n
add wave -noupdate -divider N-BIT**PARAMETER**LFSR**CNTR
add wave -noupdate -format Literal -radix hexadecimal /tb_modulo3/reg_Nbit_to_solve
add wave -noupdate -format Literal -radix hexadecimal /tb_modulo3/result_Nbit_mod3
add wave -noupdate -format Literal -radix hexadecimal /tb_modulo3/result_Nbit_mod3_calc
add wave -noupdate -format Literal -radix hexadecimal /tb_modulo3/quick_check_result_Nbit_mod3
add wave -noupdate -divider 36-BIT**FLAT**INCR**CNTR
add wave -noupdate -format Literal -radix hexadecimal /tb_modulo3/reg_36bit_to_solve
#add wave -noupdate -format Literal -radix hexadecimal /tb_modulo3/i_modulo3_36bit/second_layer_35to32
add wave -noupdate -format Literal -radix hexadecimal /tb_modulo3/result_36bit_mod3
add wave -noupdate -format Literal -radix hexadecimal /tb_modulo3/quick_check_result_36bit_mod3
add wave -noupdate -divider 36-BIT**FLAT**LFSR**CNTR
add wave -noupdate -format Literal -radix hexadecimal /tb_modulo3/reg_36bit_to_solve_lfsr
add wave -noupdate -format Literal -radix hexadecimal /tb_modulo3/result_36bit_mod3_lfsr
add wave -noupdate -format Literal -radix hexadecimal /tb_modulo3/result_36bit_mod3_calc_lfsr
add wave -noupdate -format Literal -radix hexadecimal /tb_modulo3/quick_check_result_36bit_mod3_lfsr
add wave -noupdate -divider 16-BIT**FLAT**INCR**CNTR
add wave -noupdate -format Literal -radix hexadecimal /tb_modulo3/reg_16bit_to_solve
add wave -noupdate -format Literal -radix hexadecimal /tb_modulo3/result_16bit_mod3
add wave -noupdate -format Literal -radix hexadecimal /tb_modulo3/quick_check_result_16bit_mod3
add wave -noupdate -divider 15-BIT**FLAT**INCR**CNTR
add wave -noupdate -format Literal -radix hexadecimal /tb_modulo3/reg_15bit_to_solve
add wave -noupdate -format Literal -radix hexadecimal /tb_modulo3/result_15bit_mod3
add wave -noupdate -format Literal -radix hexadecimal /tb_modulo3/quick_check_result_15bit_mod3
add wave -noupdate -divider 14-BIT**FLAT**INCR**CNTR
add wave -noupdate -format Literal -radix hexadecimal /tb_modulo3/reg_14bit_to_solve
add wave -noupdate -format Literal -radix hexadecimal /tb_modulo3/result_14bit_mod3
add wave -noupdate -format Literal -radix hexadecimal /tb_modulo3/quick_check_result_14bit_mod3
add wave -noupdate -divider 13-BIT**FLAT**INCR**CNTR
add wave -noupdate -format Literal -radix hexadecimal /tb_modulo3/reg_13bit_to_solve
add wave -noupdate -format Literal -radix hexadecimal /tb_modulo3/result_13bit_mod3
add wave -noupdate -format Literal -radix hexadecimal /tb_modulo3/quick_check_result_13bit_mod3
add wave -noupdate -divider 12-BIT**FLAT**INCR**CNTR
add wave -noupdate -format Literal -radix hexadecimal /tb_modulo3/reg_12bit_to_solve
add wave -noupdate -format Literal -radix hexadecimal /tb_modulo3/result_12bit_mod3
add wave -noupdate -format Literal -radix hexadecimal /tb_modulo3/quick_check_result_12bit_mod3
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {287145000 ps} 0}
WaveRestoreZoom {285635800 ps} {289921750 ps}
configure wave -namecolwidth 150
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 1
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0