Minimal UART Core :: Overview
Project maintainers
Details
Name: muart
Created: Mar 7, 2009
Updated: May 5, 2010
SVN Updated: No data
SVN: Browse
Latest version: download
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Other project properties
Category: Communication controller
Language: VHDL
Development status: Beta
Additional info:
FPGA proven
WishBone Compliant: No
License: LGPL
Description
This is another UART project, but is different because that it is very small and will occupy less macrocells on a CPLD.
The purpose of this core is only to implement a very basic UART, without handshaking or FIFO's.
It was developed to be syntezizable on a large number of syntesis tools, so it can be adapted to your device easily.
On the first implementation was used a Xilinx Spartan 3E, with 64 occupied slices.
Please read the documentation, it have useful implementation examples.
For the testing was used the Modelsim simulator and a Enterpoint Drigmorn board, connected with some hardware, as described on the documentation.
If this core was useful I will be very pleased if you send me some information of your project.
For bugs send me an email, as soon as possible the corrections will be done.