Configurable Parallel Scrambler
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Details
Name: parallel_scrambler
Created: Jul 29, 2014
Updated: Jul 30, 2014
SVN Updated: Jul 30, 2014
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 0 reported / 0 solved
Created: Jul 29, 2014
Updated: Jul 30, 2014
SVN Updated: Jul 30, 2014
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 0 reported / 0 solved
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Other project properties
Category:Arithmetic core
Language:VHDL
Development status:Alpha
Additional info:Design done, FPGA proven
WishBone compliant: No
WishBone version: n/a
License: LGPL
Language:VHDL
Development status:Alpha
Additional info:Design done, FPGA proven
WishBone compliant: No
WishBone version: n/a
License: LGPL
Description
This is a behavioral module for parallel scrambler/descrambler.
There are RTL scrambler modules available, the purpose of this project is to built a code that is easier to understand and more flexible for reconfiguration. The code is synthesize-able, and should not cost more than RTL modules.
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