OpenCores

PCI slave to WB master

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Details

Name: pci_to_wb
Created: Nov 9, 2011
Updated: Dec 6, 2011
SVN Updated: Dec 6, 2011
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 0 reported / 0 solved
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Other project properties

Category:System controller
Language:VHDL
Development status:Alpha
Additional info:
WishBone compliant: No
WishBone version: n/a
License: LGPL

Motivation

There are already a few cores that translate PCI bus into Wishbone bus, but none of them really worked in my project. So I took the code of the project "pci_mini" and built my own core out of it. Thanks to the original authors of pci_mini!
I'm quite new to VHDL, and this is my first big project. So I cannot guarantee that everything runs 100% smooth, but I try my best. :-)

Description

This core implements a 16 MB DWord-addressable memory image in the Wishbone bus (so WB width is 32 bit). Its functionality is reduced to the minimum which is required by the PCI specification (and I'm really trying to stick exactly to the specs).
The whole source code is contained in one file, that makes it easy to implement into a project.
It's not officially WB compatible because master arbitration is not supported.
The biggest differences to pci_mini are:
• Generally more direct and faster accesses. Reads are not delayed, but are completed in the same cycle. After finishing a PCI cycle, a next cycle could begin immediately, no additional wait time is required.
• PCI Byte Enable bits are payed regard to when reading or writing to config registers (but not when accessing memory).
• Interrupts are not supported anymore. It would be easier to connect interrupts from WB directly to the other device instead of routing it through the PCI interface.
• More comments in the code body. My goal was that everyone should be able to understand what's going on (and eventually to change the core to his own needs).

More detailed information is given in the code file.

Status

Finally! I was able to upload the file. The documentation is useless for beginners like me... :-)

Generally, the core is work in progress.
At the moment, I can work with it in my project, but there are some bugs in special cases, e.g. access at an address that doesn't belong to a WB slave etc.

Feel free to write me when you notice a mandatory PCI spec detail I haven't implemented (which is the part I'm most worried about)!