Programmable Interval Timer

Feb 10, 2010	Update to the WISHBONE interface when wait states are enabled to trade 16 data flops for 3 address registers. This change now also requires single cycle timing on the WISHBONE address bus, multi-cycle timing is still allowed on the WISHBONE write data bus. In the old design WISHBONE read cycles required the address to be decoded and the read data to be latched in the first cycle and the there was a whole cycle to drive the read data bus. The new design latches the address in the first cycle then decodes the address and outputs the data in the second cycle. (The WISHBONE bus doesn't require the address or data to be latched for multi-cycle operation but by doing this it is hoped some power will be saved in the combinational logic by reducing the decoding activity at each address change.)	Hayes, Robert
Jan 27, 2010	Change WISHBONE ack signal so no output is generated when wait states are enabled and the bus transaction is terminated in the first cycle.	Hayes, Robert
Jul 3, 2009	Cosmetic update to pit_wb_bus.v module to replace non-blocking assignments with blocking assignments in case statements.	Hayes, Robert
Jun 3, 2009	Added SINGLE_CYCLE parameter to rtl code and documentation. Fixed problem with single cycle reads.	Hayes, Robert
May 26, 2009	Fixed problem in pit_wb_bus module with the wb_wacc signal that allowed data to be written twice to the control registers. In a physical implementation slow data on the write data bus could cause bad data to be latched in the first clock cycle and then replaced by the good data at the second clock cycle.	Hayes, Robert
May 26, 2009	Updated Spec with minor corrections, Fixed "ack" signal in testbench	Hayes, Robert

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Programmable Interval Timer