## Details

Name: pyramid_unit
Created: Jul 10, 2003
Updated: Jul 17, 2003
SVN Updated: Mar 10, 2009
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## Other project properties

Category: Arithmetic core
Language:
Development status: Stable
WishBone compliant: No
WishBone version: n/a

## Description

Operation of multiplication is very important in microelectronics. Each modern microprocessor has this operation within its instruction set, and advanced microprocessors have special multiplication units, that perform multiplication during 1 synchronization period(cycle). Especially valuable multiplication is in DSP processors, where it is practically main operation. Performance of any DSP processor is defined with delays in it MAC (multiply and accumulate) unit. So efficiency of multiplication is very important.

Methodology Overview.
The idea of algorithms is as follows. Unsigned multiplicands A and D may be represented in following form: A*D = (B * 2n + ó) * (E * 2n + F), where n – any number that is satisfied with following conditions:

1. 2n 2n ó n;
2. F n.
This approach is applied recursively to all multiplicands until multiplication result may be calculated easily (for example, until multiplicands have dimension of one or two bits).

«Pyramid» algorithm.
Have a look at basic formula A*D = (B * 2n + ó) * (E * 2n + F). In case n=m-1, C and D have dimension of one bit. This basic formula is applied recursively to all further multiplicands. As a result dimension of multiplicands is decreased by one at every iteration. That is why the algorithm was named as “pyramid”.

Modified «pyramid» algorithm.
Modified «pyramid» algorithms is differ from prototype with value of n = m-2 and with dimension of operands C É D equal to 2 bits. As may be seen Modified pyramid algorithm implementation such small change gives valuable results improvement for area allocation.

## Features

"Pyramid" integer multiplication unit characteristics The algorithm was written in VHDL, synthesized within Synopsys Design Compiler on 0.35u CMOS library. The data of the allocation areas are given only for a combinational part of algorithms.

 Operands Width Delay(ns) Gates allocated 8 9.8 890 16 19.85 2815 32 37.34 10550 64 No data No data

"Optimized pyramid" multiplication IP core characteristics The algorithm was written in VHDL, synthesized within Synopsys Design Compiler on 0.35u CMOS library. The data of the allocation areas are given only for a combinational part of algorithms.

 Operands Width Delay(ns) Gates allocated 8 9.92 700 16 17.7 2300 32 33.94 8580 64 69.78 33300