RAM_wb :: Overview
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Details
Name: ram_wb
Created: Apr 24, 2009
Updated: Mar 10, 2011
SVN Updated: Apr 30, 2009
SVN: Browse
Latest version: download
Statistics: View
Other project properties
Category: Memory core
Language: Verilog
Development status: Beta
Additional info:
Design done
WishBone Compliant: Yes
License: LGPL
Overview
This is a wishbone B3 compliant RAM memory. The memory array is defined as a 32 bit memory. This gives two valuable benefits
- memory array can be mapped into one block RAM with no need for byte select during synthesis
- memory content can be initialized with CPU instructions with no need to split content into byte chunks