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Reed-Solomon Decoder (31, 19, 6) :: Overview

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Details

Name: rs_decoder_31_19_6
Created: Feb 7, 2006
Updated: Dec 1, 2011
SVN Updated: Mar 10, 2009
SVN: Browse
Latest version: download
Statistics: View

Other project properties

Category: ECC core
Language: Verilog
Development status: Stable
Additional info: Design done
WishBone compliant: No
WishBone version: n/a
License:

Specifications

- Hard-decision decoding scheme
- Codeword length (n) : 31 symbols
- Message length (k) : 19 symbols
- Error correction capability (t) : 6 symbols
- One symbol represents 5 bit
- Uses GF(2^5) with primitive polynomial p(x) = X^5 + X^2 + 1
- Generator polynomial, g(x) = a^15 + a^21*X + a^6*X^2 + a^15*X^3 + a^25*X^4 + a^17*X^5 + a^18*X^6 + a^30*X^7 + a^20*X^8 + a^23*X^9 + a^27*X^10 + a^24*X^11 + X^12. Note: a = alpha, primitive element in GF(2^5) and a^i is root of g(x) for i = 19, 20, ..., 30
- Uses Verilog description with synthesizable RTL modelling
- Consists of 5 main blocks: SC (Syndrome Computation), KES (Key Equation Solver), CSEE (Chien Search and Error Evaluator), Controller and FIFO Register

Features

- High speed decoding algorithm.
- Can output corrected received word while input new received word.
- Synchronous timing.
- dataoutstart (start of output data block) and dataoutend (end of output data block) signal to synchronize to other core outside the decoder.
- Have decoding failure flag if error is uncorrectable.

Status

- design has been simulated successfully
- uploaded v1.0
- Please do not send me email asking about all aspects of Reed-Solomon encoder-decoder (algorithms, architectures, implementation, simulation problems, etc.), since I do not provide any kind of technical supports. You can still freely download the source code though.

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