RTC in SystemVerilog :: Overview

Project maintainers


Name: rtc_systemverilog
Created: Oct 24, 2013
Updated: Apr 15, 2015
SVN: No files checked in

Other project properties

Category: System controller
Language: Verilog & VHDL
Development status: Stable
Additional info: Design done, FPGA proven
WishBone Compliant: Yes
License: LGPL


Real Time Clock with wishbone bus complaint. The RTC can transmit data to CPU as Binary Coded Decimal (BCD) values through wishbone bus. The data include the time by second, minute, hour, date, day, month, and year. It is 24-hour format. The RTC module can work with an external crystal that the frequency is not very fixed, such as 32.768kHz and so on. It also can generate two flexible interrupt requests: alarm and repetitive mode.


- BCD number: second, minute, hour, date, day, month, and year;
- Determine whether the year is leap year;
- Year 2000 problem is removed;
- Either analog crystal oscillator input or digital clock input, and clock input is not fixed;
- Repetitive interrupt mode, Programmed to provide 6 different interval interrupt requests: once per second, once per minute, once per hour, once a day, once a week, once a month;
- Alarm interrupt mode, Programmed to generate interrupt request signal when real time clock equals to the time stored beforehand in the register;
- Written in SystemVerilog, and fully synthesisable.

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