Simple General Purpose IO :: Overview
Project maintainers
Details
Name: simple_gpio
Created: Dec 2, 2002
Updated: Sep 7, 2009
SVN Updated: Mar 10, 2009
SVN: Browse
Latest version: download
Statistics: View
Other project properties
Category: Other
Language: Verilog
Development status: Stable
Additional info:
Design done, FPGA proven
WishBone Compliant: Yes
License:
Description
Simple General Purpose IO port. It supports up to 8 GPIO pins. Each pin is individually programmable as either input or output. The core features an 8bit wishbone interface. Wider wishbone interfaces are easily supported by using multiple instances (e.g. 4 simple GPIO cores provide a 32bit wishbone interface).
Very simple, very small.