部分翻译
News
| Oct 14, 2011 |
I finally started writing the documentation, hopefully will finish soon |
| May 11, 2011 |
due to no time available I have to postpone the specs doc few more months. I will probably have some spare time in July (hopefully) |
| Dec 28, 2010 |
specifications document due within end of January 2011 |
| Dec 9, 2010 |
Status brought back to planning. I'd like to rework the project structure, together with specs and design. VHDL was added as part of the project. I intend to keep the verilog source for the time being but plan to move to vhdl as soon as the status is turned to mature. |
| Dec 8, 2010 |
updating info |
| May 18, 2005 |
Changes commited to CVS |
| May 4, 2005 |
Now a "LSer"(line scheduler) is added. Each input port has a "LSer" within the Router. Each "LSer" has a routing table and all tables' content is identic(so they seems like single multi-ports memory). Little change to "eth_fifo" and a testbench is provided. |
| Apr 17, 2005 |
rtl, tb and doc files first emerge on OC's cvs.
Now i choose 16x16 buffer crossbar switch matrix for SpaceWire Router. Some pictures in *.doc and a readme.txt are also contained. All things are so rough now. |
| Apr 8, 2005 |
Project started |
© copyright 1999-2012
OpenCores.org, equivalent to ORSoC AB, all rights reserved. OpenCores®, registered trademark.