SPI with FIFO_verilog :: Overview

Project maintainers


Name: spi_with_fifo_verilog
Created: Sep 7, 2016
Updated: Jul 2, 2017
SVN: No files checked in

Other project properties

Category: Communication controller
Language: Verilog
Development status: Planning
Additional info: none
WishBone compliant: No
WishBone version: n/a
License: LGPL


This item is used for SPI output of 16-bit AD converter data signal acquisition and communication with the DSP.

© copyright 1999-2017, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.