Serial Rapid IO IP Core v2.1 :: Overview

Project maintainers


Name: srio
Created: Sep 8, 2010
Updated: Jun 14, 2017
SVN: No files checked in

Other project properties

Category: Communication controller
Language: Verilog & VHDL
Development status: Mature
Additional info: Specification done
WishBone compliant: No
WishBone version: n/a
License: LGPL


The Serial RapidIO Endpoint solution comprises a highly flexible and optimized Serial RapidIO Physical Layer core and a Logical (I/O) and Transport Layer interface. This IP solution is a netlist for RapidIO interconnect that supports x1, x4 and x8 lane widths. It comes with a configurable buffer design, reference clock module, reset module, and register manager reference design, which allows complete flexibility in selecting primitives. This solution is fully verified and supports both Verilog and VHDL design environments.

• Designed to RapidIO Interconnect Specification v2.2
• Supports x1, x4 and x8 operation with the ability to train down to x1 from x8.
• Supports speeds of 1.25, 2.5, 3.125, 5.0 and 10.0 Gbaud.

Logical Layer
• Supports a peak, unidirectional bandwidth of 32 Gbps when operating at 250 MHz.
• Concurrent Initiator and Target operations.
• Doorbell and Message support.
• 128-bit internal data path.
• Dedicated port for maintenance transactions.
• Simple handshaking mechanism to control data flow.
• Programmable source ID on all outgoing packets.
• Optional large system support for 16-bit Device IDs.

• Independently configurable TX and RX Buffer depths of 8, 16, 32 or 64 packets.
• Support for independent clocks.
• Optional TX Flow Control support.

Physical Layer
• Supports critical request flow.
• Optional support of priority-based, retransmit suppression.
• Support for multicast events.
• Supports removal of corrupted packets for error detection and initiates automatic error recovery.
• Design verified using the RapidIO Trade Association Bus Functional Model.
• For sub-features, use only as necessary.

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