srl_fifo :: Overview
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Details
Name: srl_fifo
Created: Jan 2, 2008
Updated: Feb 28, 2011
SVN Updated: Mar 10, 2009
SVN: Browse
Latest version: download
Statistics: View
Other project properties
Category: Memory core
Language: VHDL
Development status: Stable
Additional info:
Design done
WishBone Compliant: No
License: LGPL
Status
- Simulated and ( 16 and 32 ) programmed into a Spartan 3 FPGA
- Synthesised with ISE 10.1
- looking at a generic srl fifo now ise can handle such