Single Slot PCM Interface

Project maintainers

Usselmann, Rudolf

Details

Name: ss_pcm
Created: Sep 17, 2002
Updated: Feb 10, 2004
SVN Updated: Mar 10, 2009
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 0 reported / 0 solved

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Other project properties

Category:Communication controller
Language:Verilog
Development status:Stable
Additional info:FPGA proven
WishBone compliant: No
WishBone version: n/a
License:

Description

Simple PCM Interface. Allows to interface to such popular devices
like TI DSPs (via McBSP bus) in PCM mode. Of course many more
applications. Very small and simple core.

Features

- Implemented in Verilog
- Frame Start position adjustable
- full 16 bit frames
- 1 Receive holding register
- 1 Transmit holding Register
- Fully Synthesisable
- Can handle PCM streams at any rate, 128KHz to 100MHz.
- 38 LUTs in a Spartan II

Status

This core is fully functional and completed. It was tested on
a XESS XCV800 board interfacing to a proprietary device with
a TI DSP, exchanging PCM streams in both directions.

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