FIFO Queue :: Overview

Project maintainers


Name: swich_buffer
Created: Dec 16, 2010
Updated: Dec 16, 2010
SVN: No files checked in

Other project properties

Category: Memory core
Language: VHDL
Development status: Stable
Additional info: Design done, FPGA proven
WishBone Compliant: No
License: LGPL


FIFO Queues are used in switches. This core designed a buffer which is configurable in term of size and width. Size of buffer defines total number of word in buffer and width defines word size. There is also a port which returns asserts when there are specific number of free words in buffer. If free words are equal or higher than this specific number, free signal is asserted. This specific number is configurable. Buffer also has read/write/clock/reset controlling signals and has 2 buses; Data in and Data Out. Buffer can be accessed for read and write at same clock cycle, but one cycle needed to retrieve currently writing data.

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